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High Defect Coverage with Low-Power Test Sequences in a BIST Environment
September/October 2002 (vol. 19 no. 5)
pp. 44-52

A new technique, random single-input change (RSIC) test generation, generates low-power test patterns that provide a high level of defect coverage during low-power BIST of digitalcircuits. The authors propose a parallel BIST implementation of the RSIC generator and analyze its area-overhead impact.

Citation:
Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich, "High Defect Coverage with Low-Power Test Sequences in a BIST Environment," IEEE Design & Test of Computers, vol. 19, no. 5, pp. 44-52, Sept.-Oct. 2002, doi:10.1109/MDT.2002.1033791
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