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Issue No.05 - September/October (2002 vol.19)
pp: 36-43
ABSTRACT
<p>Barriers to technology scaling, such as leakage and parameter variations, challenge the effectiveness of current-based test techniques. This correlative multi-parameter test approach improves current testing sensitivity, exploiting dependencies of transistor and circuit leakage on operating frequency, temperature, and body bias to discriminate fast but intrinsically leaky ICs from defective ones.</p>
CITATION
Ali Keshavarzi, James W. Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins, "Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits", IEEE Design & Test of Computers, vol.19, no. 5, pp. 36-43, September/October 2002, doi:10.1109/MDT.2002.1033790
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