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September/October 2002 (vol. 19 no. 5)
pp. 5-7

CMOS IC scaling increases device/interconnect density to allow more logic on a die athigher clock rates,enhancing overall performance. Improvements in process technologyenable integration on a single die of circuits with different functions that require distinct manufacturing process steps. With added constraints of reduced time to market, the complexity ofCMOS ICs has grown steadily during the past few decades. Shortened development times requireshorter design, verification,and manufacturing cycles, as well as more ef .cient and accurate test and debugging methods. Despite impressive trends in the microelectronic industry,deep-submicron technologies--especially below 0.18 micron--face several important test-technology challenges. This special issue presents five articles that address some of these challenges.

Citation:
Jaume Segura, Peter Maxwell, "Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era," IEEE Design & Test of Computers, vol. 19, no. 5, pp. 5-7, Sept.-Oct. 2002, doi:10.1109/MDT.2002.1033786
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