Device scaling has long been an acceptedmantra, even an obsession, in the semiconductor industry, and if recent predictions are true, the march of deep-submicron (DSM)devicesinto the nanoscale era will continue. Process anddevice engineers will somehow find a way toovercome the looming technical challenges, justlike they always have from the earliest MOS technology days. Long-range planning, such as thatreflected in the International TechnologyRoadmap for Semiconductors, has only accelerated this trend. However, device scaling has a fundamental business purpose:either a cost advantage or a performance--and, therefore, price--advantage. At some point, the migrationof process technology nodes becomes a returnon investment (ROI)issue with direct consequences for the rest of the microelectronicsindustry. For design and test engineers, application developers, and system builders, maintaining the historic ROI for the semiconductorindustry often means doing more with less.