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A Complete Strategy for Testing an On-Chip Multiprocessor Architecture
January/February 2002 (vol. 19 no. 1)
pp. 18-28

By dividing testing into three phases-router, RAM block, and processors-this strategy ensures an efficient tradeoff of test quality and cost.

Citation:
Chouki Aktouf, "A Complete Strategy for Testing an On-Chip Multiprocessor Architecture," IEEE Design & Test of Computers, vol. 19, no. 1, pp. 18-28, Jan.-Feb. 2002, doi:10.1109/54.980050
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