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Issue No.06 - November/December (2001 vol.18)
pp: 70-79
Published by the IEEE Computer Society
This index includes all items appearing in this periodical during 2001 that are considered to have archival value. (The item title is listed only under the primary author entry in the author index.)

AUTHOR INDEX

A

Aagaard, M.D.,see Jones, R.B., July-Aug. 01, pp. 16-25.

Abadir, M.S.,see Krishnamurthy, N., July-Aug. 01, pp. 26-35.

Abadir, M.S.,see Bedsole, J., Sept.-Oct. 01, pp. 60-69.

Abraham, J.A.,see Krishnamurthy, N., July-Aug. 01, pp. 26-35.

Agarwal, V.K.,"Creating a 100-Horsepower Car without 100 Horses," Perspectives, Nov.-Dec. 01, pp. 8-9.

Aitken, R.C.,"Danger! Submicron Defects!" The Last Byte, Jan.-Feb. 01, p. 96.

Ambler, T.,and D. Wheater,"Test Trade-Offs Take Center Stage at ITC," Guest Editors' Introduction, Sept.-Oct. 01, p. 59.

Ambler, T.,see Ungar, L.Y., Sept.-Oct. 01, pp. 70-79.

Ambler, T.,"Test Strategies and Marriage Partners," The Last Byte, Sept.-Oct. 01, p. 128.

Armitage, W.D.,see Lo, J.-C., Jan.-Feb. 01, pp. 10-18.

Ashenden, P.J.,"VHDL Standards," Standards, Sept.-Oct. 01, pp. 122-123.

Austin, T.,"Design for Verification?" The Last Byte, July-Aug. 01, pp. 80, 77.

B

Bedsole, J.,et al.,"Very Low Cost Testers: Opportunities and Challenges," Sept.-Oct. 01, pp. 60-69.

Bello, D.S.S., R. Tangelder, and H. Kerkhoff,"Modeling a Verification Test System for Mixed-Signal Circuits," Jan.-Feb. 01, pp. 63-71.

Bening, L.,and H. Foster,"Optimizing Multiple EDA Tools within the ASIC Design Flow," July-Aug. 01, pp. 46-55.

Benini, L.,et al.,"Battery-Driven Dynamic Power Management," Mar.-Apr. 01, pp. 53-60.

Benso, A.,et al.,"Online and Offline BIST in IP-Core Design," Sept.-Oct. 01, pp. 92-99.

Bergamaschi, R.A.,et al.,"Automating the Design of SOCs Using Cores," Sept.-Oct. 01, pp. 32-45.

Bhattacharya, S.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Bodoni, M.L.,see Benso, A., Sept.-Oct. 01, pp. 92-99.

Borel, J.,"Potential Showstoppers in Technology and EDA Roadmaps," Perspectives, Nov.-Dec. 01, pp. 9-10.

Brakmo, L.S.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Brederlow, R.,et al.,"A Mixed-Signal Design Roadmap, Nov.-Dec. 01, pp. 34-46.

Brockmeyer, E.,see Panda, P.R., May-June 01, pp. 56-68.

Butler, K.M.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

C

Camposano, R.,"Technology Will Drive EDA's Future," Perspectives, Nov.-Dec. 01, pp. 10-11.

Carro, L.,see Ito, S.A., Sept.-Oct. 01, pp. 100-110.

Castelli, G.,see Benini, L., Mar.-Apr. 01, pp. 53-60.

Catthoor, F.,see Rajsuman, R., May-June 01, pp. 3-4.

Catthoor, F.,see Nachtergaele, L., May-June 01, pp. 40-54.

Catthoor, F.,see Panda, P.R., May-June 01, pp. 56-68.

Catthoor, F.,et al.,"Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors," May-June 01, pp. 70-82.

Catthoor, F.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Cesario, W.O.,et al.,"Colif: A Design Representation for Application-Specific Multiprocessor SOCs," Sept.-Oct. 01, pp. 8-20.

Chakrabarty, K.,see Chandra, A., Sept.-Oct. 01, pp. 80-91.

Chandra, A.,and K. Chakrabarty,"Test Resource Partitioning for SOCs," Sept.-Oct. 01, pp. 80-91.

Chandrakasan, A.,see Sinha, A., Mar.-Apr. 01, pp. 62-74.

Chandramouli, R.,see Kapur, R., Nov.-Dec. 01, pp. 47-54.

Chickermane, V.,see Zarrineh, K., May-June 01, pp. 83-97.

Chiusano, S.,see Benso, A., Sept.-Oct. 01, pp. 92-99.

Chu, B.,see Segal, J., May-June 01, pp. 28-39.

Crouch, A.,see Bedsole, J., Sept.-Oct. 01, pp. 60-69.

D

D'Amore, R.,O. Saotome, and K.H. Kienitz, "A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors," July-Aug. 01, pp. 56-64.

Danckaert, K.,see Catthoor, F., May-June 01, pp. 70-82.

Daveau, J.-M.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Davidson, S.,"Welcome to 2001," The Last Byte, Mar.-Apr. 01, p. 112.

Davidson, S.,"Debugging Using Resublimated Thiotimoline," The Last Byte, Nov.-Dec. 01, p. 80.

De Greef, E.,see Panda, P.R., May-June 01, pp. 56-68.

De Micheli, G.,see Lu, Y.-H., Mar.-Apr. 01, pp. 10-19.

Desmet, D.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Devarayanadurg, G.,see Soma, M., Jan.-Feb. 01, pp. 72-81.

Di Natale, G.,see Benso, A., Sept.-Oct. 01, pp. 92-99.

Donnay, S.,see Brederlow, R., Nov.-Dec. 01, pp. 34-46.

Drummonds, S.B.,see Venkataraman, S., Jan.-Feb. 01, pp. 19-30.

Dutt, N.D.,see Panda, P.R., May-June 01, pp. 56-68.

Dutt, N.D.,see Catthoor, F., May-June 01, pp. 70-82.

Dutta, S.,R. Jensen, and A. Rieckmann,"Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems," Sept.-Oct. 01, pp. 21-31.

Dworak, J.,et al.,"Defect-Oriented Testing and Defective-Part-Level Prediction," Jan.-Feb. 01, pp. 31-41.

E

Efthymiou, A.,see Furber, S.B., Mar.-Apr. 01, pp. 42-52.

F

Farkas, K.I.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Fellenz, C.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Foster, H.,"Applied Boolean Equivalence Verification and RTL Static Sign-Off," July-Aug. 01, pp. 6-15.

Foster, H.,see Bening, L., July-Aug. 01, pp. 46-55.

Furber, S.B.,et al.,"Power Management in the Amulet Microprocessors," Mar.-Apr. 01, pp. 42-52.

G

Garside, J.D.,see Furber, S.B., Mar.-Apr. 01, pp. 42-52.

Gauthier, L.,see Cesario, W.O., Sept.-Oct. 01, pp. 8-20.

Grimaila, M.R.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

H

Hamburgen, W.R.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Huynh, S.,see Soma, M., Jan.-Feb. 01, pp. 72-81.

I

Ishihara, T.,see Okuma, T., Mar.-Apr. 01, pp. 31-41.

Ito, S.A.,L. Carro, and R.P. Jacobi,"Making Java Work for Microcontroller Applications," Sept.-Oct. 01, pp. 100-110.

J

Jacobi, R.P.,see Ito, S.A., Sept.-Oct. 01, pp. 100-110.

Jacome, M.F.,and H.P. Peixoto,"A Survey of Digital Design Reuse," May-June 01, pp. 98-107.

Jee, A.,see Segal, J., May-June 01, pp. 28-39.

Jensen, R.,see Dutta, S., Sept.-Oct. 01, pp. 21-31.

Jerraya, A.,"Two Enduring Questions for Computer Design," The Last Byte, May-June 01, p. 128.

Jerraya, A.A.,see Wolf, W., Sept.-Oct. 01, p. 7.

Jerraya, A.A.,see Cesario, W.O., Sept.-Oct. 01, pp. 8-20.

Johnson, C.S., lII,see Lo, J.-C., Jan.-Feb. 01, pp. 10-18.

Jones, R.B.,et al.,"Practical Formal Verification in Microprocessor Design," July-Aug. 01, pp. 16-25.

Joyner, W.H., Jr.,see Kahng, A.B., Nov.-Dec. 01, pp. 4-5.

K

Kahng, A.B.,and W.H. Joyner Jr., "Roadmaps and Visions for Design and Test," Guest Editors' Introduction," Nov.-Dec. 01, pp. 4-5.

Kapur, R.,R. Chandramouli, and T.W. Williams, "Strategies for Low-Cost Test," Nov.-Dec. 01, pp. 47-54.

Kaul, H.,see Sylvester, D., Nov.-Dec. 01, pp. 12-22.

Keitel-Schulz, D.,and N. When,"Embedded DRAM Development: Technology, Physical Design, and Application Issues," May-June 01, pp. 7-15.

Kerkhoff, H.,see Bello, D.S.S., Jan.-Feb. 01, pp. 63-71.

Keutzer, K.,see Tasiran, S., July-Aug. 01, pp. 36-45.

Keutzer, K.,"Bright Future for Programmable Processors," Perspectives, Nov.-Dec. 01, pp. 7-8.

Kienitz, K.H.,see D'Amore, R., July-Aug. 01, pp. 56-64.

Kim, J.,see Shin, D., Mar.-Apr. 01, pp. 20-30.

Kim, S.,see Soma, M., Jan.-Feb. 01, pp. 72-81.

Krishnamurthy, N.,et al.,"Design and Development Paradigm for Industrial Formal Verification CAD Tools," July-Aug. 01, pp. 26-35.

Kulkarni, C.,see Nachtergaele, L., May-June 01, pp. 40-54.

Kulkarni, C.,see Panda, P.R., May-June 01, pp. 56-68.

L

Lauwereins, R.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Lee, S.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

Lee, S.,see Shin, D., Mar.-Apr. 01, pp. 20-30.

Lee, W.R.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Lepejian, D.,see Segal, J., May-June 01, pp. 28-39.

Lewis, M.J.G.,see Furber, S.B., Mar.-Apr. 01, pp. 42-52.

Lloyd, D.W.,see Furber, S.B., Mar.-Apr. 01, pp. 42-52.

Lo, J.-C.,W.D. Armitage, and C.S. Johnson III,"Using Atomic Force Microscopy for Deep Submicron Failure Analysis," Jan.-Feb. 01, pp. 10-18.

Lombardi, F.,and C. Metra,"Defect-Oriented Diagnosis for Very Deep-Submicron Systems," Guest Editors' Introduction, Jan.-Feb. 01, pp. 8-9.

Lu, Y.-H.,and G. De Micheli,"Comparing System Level Power Management Policies," Mar.-Apr. 01, pp. 10-19.

Lyonnard, D.,see Cesario, W.O., Sept.-Oct. 01, pp. 8-20.

M

Macii, A.,see Benini, L., Mar.-Apr. 01, pp. 53-60.

Macii, E.,et al.,"Dynamic Power Management of Electronic Systems," Guest Editor's Introduction, Mar.-Apr. 01, pp. 6-9.

Maly, W.,"The Design and Test Cost Problem," Perspectives, Nov.-Dec. 01, p. 6.

Marchal, P.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Martin, A.K.,see Krishnamurthy, N., July-Aug. 01, pp. 26-35.

Martin, G.,see Sangiovanni-Vincentelli, A., Nov.-Dec. 01, pp. 23-33.

Melham, T.F.,see Jones, R.B., July-Aug. 01, pp. 16-25.

Mercer, M.R.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

Metra, C.,see Lombardi, F., Jan.-Feb. 01, pp. 8-9.

Muhammad, K.,and K. Roy,"Fault Detection and Location Using I DD Waveform Analysis," Jan.-Feb. 01, pp. 42-49.

Muhlada, M.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

N

Nachtergaele, L.,F. Catthoor, and C. Kulkarni,"Random-Access Data Storage Components in Customized Architectures," May-June 01, pp. 40-54.

Nicolau, A.,see Panda, P.R., May-June 01, pp. 56-68.

Nicolescu, G.,see Cesario, W.O., Sept.-Oct. 01, pp. 8-20.

O

Okuma, T.,H. Yasuura, and T. Ishihara,"Software Energy Reduction Techniques for Variable-Voltage Processors," Mar.-Apr. 01, pp. 31-41.

O'Leary, J.W.,see Jones, R.B., July-Aug. 01, pp. 16-25.

Panda, P.R.,et al.,"Data Memory Organization and Optimizations in Application-Specific Systems," May-June 01, pp. 56-68.

P

Peixoto, H.P.,see Jacome, M.F., May-June 01, pp. 98-107.

Pixley, C.,"Formal Verification of Commercial Integrated Circuits," Guest Editor's Introduction, July-Aug. 01, pp. 4-5.

Plusquellic, J.,"IC Diagnosis Using Multiple Supply Pad IDDQs," Jan.-Feb. 01, pp. 50-61.

Prinetto, P.,see Benso, A., Sept.-Oct. 01, pp. 92-99.

R

Raina, R.,see Bedsole, J., Sept.-Oct. 01, pp. 60-69.

Rajsuman, R.,and F. Catthoor,"The New World of Large Embedded Memories," Guest Editors' Introduction, May-June 01, pp. 3-4.

Rajsuman, R.,"Design and Test of Large Embedded Memories: An Overview," May-June 01, pp. 16-27.

Rieckmann, A.,see Dutta, S., Sept.-Oct. 01, pp. 21-31.

Roy, K.,see Muhammad, K., Jan.-Feb. 01, pp. 42-49.

S

Sachdev, M.,"Current-Based Testing for Deep-Submicron VLSIs," Mar.-Apr. 01, pp. 76-84.

Sangiovanni-Vincentelli, A.,and G. Martin,"Platform-Based Design and Software Design Methodology for Embedded Systems," Nov.-Dec. 01, pp. 23-33.

Saotome, O.,see D'Amore, R., July-Aug. 01, pp. 56-64.

Sauerer, J.,see Brederlow, R., Nov.-Dec. 01, pp. 34-46.

Scarsi, R.,see Benini, L., Mar.-Apr. 01, pp. 53-60.

Segal, J.,et al.,"Using Electrical Bitmap Results from Embedded Memory to Enhance Yield," May-June 01, pp. 28-39.

Seger, C.-J.H.,see Jones, R.B., July-Aug. 01, pp. 16-25.

Shin, D.,J. Kim, and S. Lee,"Intra-Task Voltage Scheduling for Low-Energy Hard Real-Time Applications," Mar.-Apr. 01, pp. 20-30.

Shubat, A.,"Moving the Market to Embedded Memory," Perspectives, May-June 01, pp. 5-6.

Simunic, T.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Sinha, A.,and A. Chandrakasan,"Dynamic Power Management in Wireless Sensor Networks," Mar.-Apr. 01, pp. 62-74.

Sylvester, D.,and H. Kaul,"Power-Driven Challenges in Nanometer Design," Nov.-Dec. 01, pp. 12-22.

Smith, M.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Soma, M.,et al.,"Hierarchical ATPG for Analog Circuits and Systems," Jan.-Feb. 01, pp. 72-81.

Sprachmann, M.,"Automatic Generation of Parallel CRC Circuits," May-June 01, pp. 108-114.

Stanley, K.,"High-Accuracy Flush-and-Scan Software Diagnostic," Nov.-Dec. 01, pp. 56-62.

Stewart, B.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

Stora, M.,Standards, Mar.-Apr. 01, p. 95.

T

Tangelder, R.,see Bello, D.S.S., Jan.-Feb. 01, pp. 63-71.

Tasiran, S.,and K. Keutzer,"Coverage Metrics for Functional Validation of Hardware Designs," July-Aug. 01, pp. 36-45.

Temple, S.,see Furber, S.B., Mar.-Apr. 01, pp. 42-52.

U

Ungar, L.Y.,and T. Ambler,"Economics of Built-in Self-Test," Sept.-Oct. 01, pp. 70-79.

Upadhyaya, S.J.,see Zarrineh, K., May-June 01, pp. 83-97.

V

Vandecappelle, A.,see Panda, P.R., May-June 01, pp. 56-68.

Venkataraman, S.,and S.B. Drummonds,"Poirot: Applications of a Logic Fault Diagnosis Tool," Jan.-Feb. 01, pp. 19-30.

Verkest, D.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Vertregt, M.,see Brederlow, R., Nov.-Dec. 01, pp. 34-46.

Viredaz, M.A.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

W

Wagner, R.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Wallach, D.A.,see Macii, E., Mar.-Apr. 01, pp. 6-9.

Wamback, P.,see Brederlow, R., Nov.-Dec. 01, pp. 34-46.

Wang, L.-C.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

Weber, W.,see Brederlow, R., Nov.-Dec., pp. 34-46.

Wehn, N.,see Keitel-Schulz, D., May-June 01, pp. 7-15.

Wheater, D.,see Ambler, T., Sept.-Oct. 01, p. 59.

White, F.,see Bergamaschi, R.A., Sept.-Oct. 01, pp. 32-45.

Wicker, J.D.,see Dworak, J., Jan.-Feb. 01, pp. 31-41.

Williams, T.W.,see Kapur, R., Nov.-Dec. 01, pp. 47-54.

Wolf, W.,and A.A. Jerraya,"Application-Specific System-on-a-Chip Multiprocessors," Guest Editors' Introduction, Sept.-Oct. 01, p. 7.

Wong, C.,see Yang, P., Sept.-Oct. 01, pp. 46-58.

Wuytack, S.,see Catthoor, F., May-June 01, pp. 70-82.

Y

Yang, P.,et al.,"Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs," Sept.-Oct. 01, pp. 46-58.

Yasuura, H.,see Okuma, T., Mar.-Apr. 01, pp. 31-41.

Z

Zarrineh, K.,S.J. Upadhyaya, and V. Chickermane,"System-on-Chip Testability Using LSSD Scan Structures," May-June 01, pp. 83-97.

Zhang, J.,see Soma, M., Jan.-Feb. 01, pp. 72-81.

Zorian, Y.," D&T and the Future," From the EIC, Jan.-Feb. 01, p. 1.

Zorian, Y.,"Managing Power," From the EIC, Mar.-Apr. 01, p. 1.

Zorian, Y.,"Huge Storage Capacity," From the EIC, May-June 01, p. 1.

Zorian, Y.,"Error-Free Products," From the EIC, July-Aug. 01, p. 2.

Zorian, Y.,"Optimal Processing Resources," From the EIC, Sept.-Oct. 01, p. 1.

Zorian, Y.,"Forecasting and Planning," From the EIC, Nov.-Dec. 01, p. 3.

SUBJECT INDEX

A
Algorithm theory

dynamic power management in wireless sensor networks, A. Sinha et al., Mar.-Apr. 01, pp. 62-74.

Analog circuits

hierarchical ATPG for analog circuits/systems, M. Soma et al., Jan.-Feb. 01, pp. 72-81.

Application-specific ICs

bright future for programmable processors, Perspectives, K. Keutzer, Nov.-Dec. 01, pp. 7-8.

digital design reuse, survey, M.F. Jacome et al., May-June 01, pp. 98-107.

multiple EDA tools within ASIC design flow, L. Bening et al., July-Aug. 01, pp. 46-55.

Atomic force microscopy

deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

Automatic test equipment

test trade-offs, issues covered at 2001 International Test Conference (ITC), Special Issue, Sept.-Oct. 01, pp. 59-99.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

Automatic test pattern generation

hierarchical ATPG for analog circuits/systems, M. Soma et al., Jan.-Feb. 01, pp. 72-81.

B
Boolean functions

applied Boolean equivalence verification and RTL static sign-off, H. Foster, July-Aug. 01, pp. 6-15.

Boundary scan testing

SOC testability using LSSD scan structures, K. Zarrineh et al., May-June 01, pp. 83-97.

Buffer storage

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, Rajsuman, R., et al., May-June 01, pp. 3-4.

Built-in self test

economics of BIST, L.Y. Ungar et al., Sept.-Oct. 01, pp. 70-79.

online/offline BIST in IP-core design, A. Benso et al., Sept.-Oct. 01, pp. 92-99.

C
CAD,
see Electronic design automation, Logic CAD
Cellular logic

design closure with cell-based systems, Roundtable, Sept.-Oct. 01, pp. 112-119.

Circuit analysis computing,
see Circuit simulation.
Circuit CAD

digital design reuse, survey, M.F. Jacome et al., May-June 01, pp. 98-107.

Circuit complexity

hierarchical ATPG for analog circuits/systems, M. Soma et al., Jan.-Feb. 01, pp. 72-81.

verification test system. modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

Circuit layout CAD

design closure with cell-based systems, Roundtable, Sept.-Oct. 01, pp. 112-119.

Circuit optimization

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

Circuit reliability,
see IC reliability.
Circuit simulation

mixed-signal circuits, verification test system modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

Circuit testing

AFM for deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

Circuit testing,
see IC testing.
C++ language

SOC specification and modeling using C++ language, challenges and opportunities, Roundtable, May-June 01, pp. 115-123.

CMOS ICs

current-based testing for deep-submicron VLSIs, M. Sachdev, Mar.-Apr. 01, pp. 76-84.

Computational complexity

digital design reuse, survey, M.F. Jacome et al., May-June 01, pp. 98-107.

Computer architecture

bit-scalable architecture for fuzzy processors, R. D'Amore et al., July-Aug. 01, pp. 56-64.

Computer architecture,
see Memory architecture, Reconfigurable architectures, Reduced instruction set computing.
Computer design

two enduring questions for computer design (complexity and memory), A. Jerraya, The Last Byte, May-June 01, p. 128.

Computer peripheral equipment,
see Digital storage.
Computer power supplies

Amulet microprocessors, power management, S.B. Furber et al., Mar.-Apr. 01, pp. 42-52.

battery-driven dynamic power management, L. Benini et al., Mar.-Apr. 01, pp. 53-60.

intra-task voltage scheduling for low-energy hard real-time applications, D. Shin et al., Mar.-Apr. 01, pp. 20-30.

software energy reduction techs. for variable-voltage processors, T. Okuma et al., Mar.-Apr. 01, pp. 31-41.

system-level power management policies, Y.-H. Lu et al., Mar.-Apr. 01, pp. 10-19.

Concurrency control,
see VHDL.
Controllability

hierarchical ATPG for analog circuits/systems, M. Soma et al., Jan.-Feb. 01, pp. 72-81.

Control theory,
see Controllability, Observability.
D
Data communication

automatic generation of parallel CRC circuits, M. Sprachmann, May-June 01, pp. 108-114.

Data handling,
see Multimedia computing.
Debugging

failure latency in debugging, The Last Byte, S. Davidson, Nov.-Dec. 01, p. 80.

Deep-submicron technology

AFM for deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

current-based testing for deep-submicron VLSIs, M. Sachdev, Mar.-Apr. 01, pp. 76-84.

deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

defects in deep-submicron tests, R.C. Aitken, The Last Byte, Jan.-Feb. 01, p. 96.

design and test cost problem, Perspectives, W. Maly, Nov.-Dec. 01, p. 6.

Defects,
see Submicron defects.
Design for testability

test strategies and marriage partners, T. Ambler, The Last Byte, Sept.-Oct. 01, p. 128.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Special Issue, Sept.-Oct. 01, pp. 59-99.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

very low cost testers, J. Bedsole et al., Sept.-Oct. 01, pp. 60-69.

Diagnosis

D&T and the future, Y. Zorian, From the EIC, Jan.-Feb. 01, p. 1.

Diagnostics

high-accuracy flush-and-scan software diagnostic, K. Stanley, Nov.-Dec. 01, pp. 56-62.

Digital computers,
see Microcomputers.
Digital ICs,
see Integrated logic circuits, Integrated memory circuits, Microprocessor chips.
Digital storage

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, Rajsuman, R., et al., May-June 01, pp. 3-4.

Digital storage,
see Buffer storage, Random-access storage, Semiconductor storage.
Digital systems,
see Multiprocessing systems.
Digital television

Viper, multiprocessor SOC for advanced set-top box and digital TV systems, S. Dutta et al., Sept.-Oct. 01, pp. 21-31.

Disruptive technologies

embedded test will eventually become mainstream, Perspectives, V.K. Agarwal, Nov.-Dec. 01, pp. 8-9.

Distributed processing

adding reconfigurable logic to SOC designs, Roundtable, July-Aug. 01, pp. 65-71.

Distributed processing,
see Multiprocessing systems, Parallel processing.
Divide-and-conquer methods

Colif, design representation for application-specific multiprocessor SOCs, W.O. Cesario et al., Sept.-Oct. 01, pp. 8-20.

DRAM chips

embedded DRAM development, technology, physical design, and application issues, D. Keitel-Schulz et al., May-June 01, pp. 7-15.

E
Economics,
see IC economics.
Electrical faults,
see Fault location.
Electric variables control,
see Voltage control.
Electron device testing,
see Semiconductor device testing.
Electronic design automation

automated design of SOCs using cores, R.A. Bergamaschi et al., Sept.-Oct. 01, pp. 32-45.

design closure with cell-based systems, Roundtable, Sept.-Oct. 01, pp. 112-119.

embedded memories, design and test, R. Rajsuman, May-June 01, pp. 16-27.

technology will drive EDA's future, Perspectives, R. Camposano, Nov.-Dec. 01, pp. 10-11.

Electronic design automation,
see Circuit CAD, Circuit layout CAD.
Electronic engineering,
see Low-power electronics.
Electronic engineering computing,
see Electronic design automation, Logic CAD, Logic simulation, SPICE.
Electronic equipment testing,
see Circuit testing.
Electronic packaging,
see IEEE standards.
Electronic systems

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

Embedded systems

customized memory organization, application-specific designs, P.R. Panda et al., May-June 01, pp. 56-68.

embedded DRAM development, technology, physical design, and application issues, D. Keitel-Schulz et al., May-June 01, pp. 7-15.

energy-aware runtime scheduling for embedded multiprocessor SOCs, P. Yang et al., Sept.-Oct. 01, pp. 46-58.

Java machine, microcontroller applications, S.A. Ito et al., Sept.-Oct. 01, pp. 100-110.

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, R. Rajsuman et al., May-June 01, pp. 3-4.

platform-based design and software design methodology for embedded systems, A. Sangiovanni-Vincentelli and G. Martin, Nov.-Dec. 01, pp. 23-33.

SOCs, embedded memory, Perspectives, A. Shubat, May-June 01, pp. 5-6.

Embedded test

embedded test will eventually become mainstream, Perspectives, V.K. Agarwal, Nov.-Dec. 01, pp. 8-9.

Error detection

automatic generation of parallel CRC circuits, M. Sprachmann, May-June 01, pp. 108-114.

F
Failure analysis

AFM for deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

bitmap results from embedded memory, yield enhancement, J. Segal et al., May-June 01, pp. 28-39.

Fault diagnosis

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

defect-oriented testing and defective-part-level prediction, J. Dworak et al., Jan.-Feb. 01, pp. 31-41.

Poirot, logic fault diagnosis tool, S. Venkataraman et al., Jan.-Feb. 01, pp. 19-30.

Fault diagnosis,
see Fault location.
Fault location

IDD waveform analysis for fault detection and location, K. Muhammad et al., Jan.-Feb. 01, pp. 42-49.

multiple supply pad IDDQs for IC diagnosis, J. Plusquellic, Jan.-Feb. 01, pp. 50-61.

Fault-tolerant computing

adding reconfigurable logic to SOC designs, Roundtable, July-Aug. 01, pp. 65-71.

Field-programmable gate arrays

adding reconfigurable logic to SOC designs, Roundtable, July-Aug. 01, pp. 65-71.

Java machine, microcontroller applications, S.A. Ito et al., Sept.-Oct. 01, pp. 100-110.

Formal logic,
see Boolean functions, Cellular logic.
Formal specification

SOC specification and modeling using C++, challenges and opportunities, Roundtable, May-June 01, pp. 115-123.

Formal verification

applied Boolean equivalence verification and RTL static sign-off, H. Foster, July-Aug. 01, pp. 6-15.

design for verification, T. Austin, July-Aug. 01, pp. 80, 77,

coverage metrics for functional validation of hardware designs, S. Tasiran et al., July-Aug. 01, pp. 36-45.

error-free products, Y. Zorian, From the EIC, July-Aug. 01, p. 2.

formal verification of commercial ICs, Special Issue, July-Aug. 01, pp. 4-45.

formal verification of commercial ICs, Guest Editor's Introduction, C. Pixley, July-Aug. 01, pp. 4-5.

mixed-signal circuits, verification test system modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

microprocessor design using formal verification methodology, R.B. Jones et al., July-Aug. 01, pp. 16-25.

Versys2, formal verification CAD tool, N. Krishnamurthy et al., July-Aug. 01, pp. 26-35.

Functions,
see Boolean functions.
G
Geometric regularity

design and test cost problem, Perspectives, W. Maly, Nov.-Dec. 01, p. 6.

Government policies,
see Research initiatives.
H
Hardware description languages

automatic generation of parallel CRC circuits, M. Sprachmann, May-June 01, pp. 108-114.

multiple EDA tools within ASIC design flow, L. Bening et al., July-Aug. 01, pp. 46-55.

VHDL standards, P.J. Ashenden, Standards, Sept.-Oct. 01, pp. 122-123.

Hewlett, William R.

Obituary. Jan.-Feb. 01, p. 6.

High level synthesis

automated design of SOCs using cores, R.A. Bergamaschi et al., Sept.-Oct. 01, pp. 32-45.

Colif, design representation for application-specific multiprocessor SOCs, W.O. Cesario et al., Sept.-Oct. 01, pp. 8-20.

Java machine, microcontroller applications, S.A. Ito et al., Sept.-Oct. 01, pp. 100-110.

I
IEEE standards

IEEE P1552 electronic-packaging standard, M.J. Stora, Standards, p. 95.

VHDL standards, P.J. Ashenden, Standards, Sept.-Oct. 01, pp. 122-123.

IC design

design and test issues posed by single-chip multiprocessors, Roundtable, Jan.-Feb. 01, pp. 82-89.

design closure with cell-based systems, Roundtable, Sept.-Oct. 01, pp. 112-119.

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

embedded DRAM development: technology, physical design, and application issues, D. Keitel-Schulz et al., May-June 01, pp. 7-15.

IC economics

economics of BIST, L.Y. Ungar et al., Sept.-Oct. 01, pp. 70-79.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Special Issue, Sept.-Oct. 01, pp. 59-99,

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59,

IC manufacturing,
see IC economics.
IC modeling

SOC specification and modeling using C++, challenges and opportunities, Roundtable, May-June 01, pp. 115-123.

IC reliability

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

formal verification of commercial ICs, Special Issue, July-Aug. 01, pp. 4-45.

formal verification of commercial ICs, Guest Editor's Introduction, C. Pixley, July-Aug. 01, pp. 4-5.

IC technology

embedded DRAM development: technology, physical design, and application issues, D. Keitel-Schulz et al., May-June 01, pp. 7-15.

IC testing

bitmap results from embedded memory, yield enhancement, J. Segal et al., May-June 01, pp. 28-39.

current-based testing for deep-submicron VLSIs, M. Sachdev, Mar.-Apr. 01, pp. 76-84.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editor's Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

defect-oriented testing and defective-part-level prediction, J. Dworak et al., Jan.-Feb. 01, pp. 31-41.

design and test issues posed by single-chip multiprocessors, Roundtable, Jan.-Feb. 01, pp. 82-89.

embedded memories, design and test, R. Rajsuman, May-June 01, pp. 16-27.

formal verification of commercial ICs, Special Issue, July-Aug. 01, pp. 4-45.

formal verification of commercial ICs, Guest Editor's Introduction, C. Pixley, July-Aug. 01, pp. 4-5.

IDD waveform analysis for fault detection and location, K. Muhammad, et al., Jan.-Feb. 01, pp. 42-49.

mixed-signal circuits, verification test system modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

multiple supply pad IDDQs for IC diagnosis, J. Plusquellic, Jan.-Feb. 01, pp. 50-61.

SOC testability using LSSD scan structures, K. Zarrineh et al., May-June 01, pp. 83-97.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Special Issue, Sept.-Oct. 01, pp. 59-99.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

very low cost testers, J. Bedsole et al., Sept.-Oct. 01, pp. 60-69.

Integrated logic circuits

application-specific SOC multiprocessors, Special Issue, Sept.-Oct. 01, pp. 7-58.

application-specific SOC multiprocessors, Guest Editors' Introduction, W. Wolf et al., Sept.-Oct. 01, p. 7.

design closure with cell-based systems, Roundtable, Sept.-Oct. 01, pp. 112-119.

Integrated memory circuits

bitmap results from embedded memory, yield enhancement, J. Segal et al., May-June 01, pp. 28-39.

embedded memories, design and test, R. Rajsuman, May-June 01, pp. 16-27.

SOCs, embedded memory, Perspectives, A. Shubat, May-June 01, pp. 5-6.

Integrated memory circuits,
see DRAM chips.
J
Java

Java machine, microcontroller applications, S.A. Ito et al., Sept.-Oct. 01, pp. 100-110.

L
Languages,
see Specification languages.
Large scale integration,
see VLSI.
Logic CAD

coverage metrics for functional validation of hardware designs, S. Tasiran et al., July-Aug. 01, pp. 36-45.

multiple EDA tools within ASIC design flow, L. Bening et al., July-Aug. 01, pp. 46-55.

Poirot, logic fault diagnosis tool, S. Venkataraman et al., Jan.-Feb. 01, pp. 19-30.

Versys2, formal verification CAD tool, N. Krishnamurthy et al., July-Aug. 01, pp. 26-35.

Logic circuits

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

Logic circuits,
see Integrated logic circuits.
Logic design

application-specific SOC multiprocessors, Special Issue, Sept.-Oct. 01, pp. 7-58.

application-specific SOC multiprocessors, Guest Editors' Introduction, W. Wolf et al., Sept.-Oct. 01, p. 7.

applied Boolean equivalence verification and RTL static sign-off, H. Foster, July-Aug. 01, pp. 6-15.

automatic generation of parallel CRC circuits, M. Sprachmann, May-June 01, pp. 108-114.

bit-scalable architecture for fuzzy processors, R. D'Amore et al., July-Aug. 01, pp. 56-64.

microprocessor design using formal verification methodology, R.B. Jones et al., July-Aug. 01, pp. 16-25.

Logic design,
see Logic partitioning.
Logic devices,
see Logic circuits.
Logic partitioning

Poirot, logic fault diagnosis tool, S. Venkataraman et al., Jan.-Feb. 01, pp. 19-30.

Logic simulation

coverage metrics for functional validation of hardware designs, S. Tasiran et al., July-Aug. 01, pp. 36-45.

Logic testing

coverage metrics for functional validation of hardware designs, S. Tasiran et al., July-Aug. 01, pp. 36-45.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

defect-oriented testing and defective-part-level prediction, J. Dworak et al., Jan.-Feb. 01, pp. 31-41.

IDD waveform analysis for fault detection and location, K. Muhammad et al., Jan.-Feb. 01, pp. 42-49.

multiple supply pad IDDQs for IC diagnosis, J. Plusquellic, Jan.-Feb. 01, pp. 50-61.

test resource partitioning for SOCs, A. Chandra et al., Sept.-Oct. 01, pp. 80-91.

Low-cost test

strategies for low-cost test, R. Kapur et al., Nov.-Dec. 01, pp. 47-54.

Low-power electronics

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

M
Management,
see Project management, Research and development management.
Memory,
see Computer design.
Memory architecture

code transformations for data transfer and storage in multimedia processors, F. Catthoor et al., May-June 01, pp. 70-82.

customized data storage, design choices, L. Nachtergaele et al., May-June 01, pp. 40-54.

customized memory organization, application-specific designs, P.R. Panda et al., May-June 01, pp. 56-68.

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, R. Rajsuman et al., May-June 01, pp. 3-4.

Microcomputers

Amulet microprocessors, power management, S.B. Furber et al., Mar.-Apr. 01, pp. 42-52.

Microcomputers,
see Portable computers.
Microcontrollers

Java machine, microcontroller applications, S.A. Ito et al., Sept.-Oct. 01, pp. 100-110.

Micromechanical devices,
see Microsensors.
Microprocessor chips

automated design of SOCs using cores, R.A. Bergamaschi et al., Sept.-Oct. 01, pp. 32-45.

bit-scalable architecture for fuzzy processors, R. D'Amore et al., July-Aug. 01, pp. 56-64.

Colif, design representation for application-specific multiprocessor SOCs, W.O. Cesario et al., Sept.-Oct. 01, pp. 8-20.

design and test issues posed by single-chip multiprocessors, Roundtable, Jan.-Feb. 01, pp. 82-89.

microprocessor design using formal verification methodology, R.B. Jones et al., July-Aug. 01, pp. 16-25.

SOCs, embedded memory, Perspectives, A. Shubat, May-June 01, pp. 5-6.

test resource partitioning for SOCs, A. Chandra et al., Sept.-Oct. 01, pp. 80-91.

Viper, multiprocessor SOC for advanced set-top box and digital TV systems, S. Dutta et al., Sept.-Oct. 01, pp. 21-31.

Microsensors

dynamic power management in wireless sensor networks, A. Sinha et al., Mar.-Apr. 01, pp. 62-74.

Mixed analog/digital ICs

mixed-signal circuits, verification test system modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

Mixed-signal design

mixed-signal design roadmap, R. Brederlow et al., Nov.-Dec. 01, pp. 34-46.

Modeling,
see IC modeling.
Moore's Law

design and test cost problem, Perspectives, W. Maly, Nov.-Dec. 01, p. 6.

Multimedia computing

code transformations for data transfer and storage in multimedia processors, F. Catthoor et al., May-June 01, pp. 70-82.

Multiprocessing systems

application-specific SOC multiprocessors, Special Issue, Sept.-Oct. 01, pp. 7-58.

application-specific SOC multiprocessors, Guest Editors' Introduction, W. Wolf et al., Sept.-Oct. 01, p. 7.

Colif, design representation for application-specific multiprocessor SOCs, W.O. Cesario et al., Sept.-Oct. 01, pp. 8-20.

design and test issues posed by single-chip multiprocessors, Roundtable, Jan.-Feb. 01, pp. 82-89.

Viper, multiprocessor SOC for advanced set-top box and digital TV systems, S. Dutta et al., Sept.-Oct. 01, pp. 21-31.

N
Nanometer design

power-driven challenges in nanometer design, D. Sylvester et al., Nov.-Dec. 01, pp. 12-22.

Network synthesis,
see Circuit CAD, Circuit optimization, IC design.
O
Obituaries

William R. Hewlett. Jan.-Feb. 01, p. 6.

Object-oriented languages,
see C++ language.
Observability

hierarchical ATPG for analog circuits/systems, M. Soma et al., Jan.-Feb. 01, pp. 72-81.

Optimization,
see Circuit optimization.
P
Packaging,
see IEEE standards.
Parallel processing

design and test issues posed by single-chip multiprocessors, Roundtable, Jan.-Feb. 01, pp. 82-89.

Performance evaluation

system-level power management policies, Y.-H. Lu et al., Mar.-Apr. 01, pp. 10-19.

Platform-based design

platform-based design and software design methodology for embedded systems, A. Sangiovanni-Vincentelli and G. Martin, Nov.-Dec. 01, pp. 23-33.

Portable computers

battery-driven dynamic power management, L. Benini et al., Mar.-Apr. 01, pp. 53-60.

Power consumption

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

intra-task voltage scheduling for low-energy hard real-time applications, D. Shin et al., Mar.-Apr. 01, pp. 20-30.

managing power, Y. Zorian, From the EIC, Mar.-Apr. 01, p. 1.

power-driven challenges in nanometer design, D. Sylvester et al., Nov.-Dec. 01, pp. 12-22.

software energy reduction technologies for variable-voltage processors, T. Okuma et al., Mar.-Apr. 01, pp. 31-41.

system-level power management policies, Y.-H. Lu et al., Mar.-Apr. 01, pp. 10-19.

Power supplies to apparatus,
see Computer power supplies.
Processing resources

optimizing SOC design and resource optimization for testing complex SOCs, Y. Zorian, From the EIC, Sept.-Oct. 01, p. 1.

Program compilers

code transformations for data transfer and storage in multimedia processors, F. Catthoor et al., May-June 01, pp. 70-82.

Programmable processors

bright future for programmable processors, Perspectives, K. Keutzer, Nov.-Dec. 01, pp. 7-8.

Program testing,
see Formal verification.
Project management

industry and university test research collaboration, Roundtable, Mar.-Apr. 01, pp. 98-105.

Pulse circuits,
see Logic circuits.
R
Radio access networks

dynamic power management in wireless sensor networks, A. Sinha et al., Mar.-Apr. 01, pp. 62-74.

Random-access storage

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, R. Rajsuman et al., May-June 01, pp. 3-4.

Random-access storage,
see DRAM chips.
Real-time systems,
see Embedded systems.
Reconfigurable architectures

adding reconfigurable logic to SOC designs, Roundtable, July-Aug. 01, pp. 65-71.

Reduced-instruction-set computing

Amulet microprocessors, power management, S.B. Furber et al., Mar.-Apr. 01, pp. 42-52.

Reliability,
see Fault-tolerant computing, Semiconductor device reliability.
Research and development management

industry and university test research collaboration, Roundtable, Mar.-Apr. 01, pp. 98-105.

Research initiatives

industry and university test research collaboration, Roundtable, Mar.-Apr. 01, pp. 98-105.

Reuse

design and test cost problem, Perspectives, W. Maly, Nov.-Dec. 01, p. 6.

Roadmaps

bright future for programmable processors, Perspectives, K. Keutzer, Nov.-Dec. 01, pp. 7-8.

design and test cost problem, Perspectives, W. Maly, Nov.-Dec. 01, p. 6.

embedded test will eventually become mainstream, Perspectives, V.K. Agarwal, Nov.-Dec. 01, pp. 8-9.

forecasting and planning, From the EIC, Y. Zorian, Nov.-Dec. 01, p. 3.

identifying potential showstoppers, Perspectives, J. Borel, Nov.-Dec. 01, pp. 9-10.

mixed-signal design roadmap, R. Brederlow et al., Nov.-Dec. 01, pp. 34-46.

roadmaps and visions for design and test, Special Issue, Nov.-Dec. 01, pp. 4-54.

roadmaps and visions for design and test, Guest Editors' Introduction, A. Kahng et al., pp. 4-5.

technology will drive EDA's future, Perspectives, R. Camposano, Nov.-Dec. 01, pp. 10-11.

S
Scanning probe microscopy,
see Atomic force microscopy.
Scheduling

energy-aware runtime scheduling for embedded multiprocessor SOCs, P. Yang et al., Sept.-Oct. 01, pp. 46-58.

Semiconductor device reliability

formal verification of commercial ICs, Special Issue, July-Aug. 01, pp. 4-45.

formal verification of commercial ICs, Guest Editor's Introduction, C. Pixley, July-Aug. 01, pp. 4-5.

Semiconductor device testing

test trade-offs, issues covered at 2001 International Test Conference (ITC), Special Issue, Sept.-Oct. 01, pp. 59-99.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

Semiconductor storage

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, R. Rajsuman et al., May-June 01, pp. 3-4.

Semiconductor storage,
see Integrated memory circuits.
Sensors,
see Microsensors.
Showstoppers

identifying potential showstoppers, Perspectives, J. Borel, Nov.-Dec. 01, pp. 9-10.

Silicon debugging,
see Debugging.
Simulation,
see Circuit simulation, Logic simulation.
Software design

platform-based design and software design methodology for embedded systems, A. Sangiovanni-Vincentelli and G. Martin, Nov.-Dec. 01, pp. 23-33.

Software diagnostic,
see Diagnostics
Software engineering,
see Formal specification, Formal verification.
Special issues and sections

application-specific SOC multiprocessors, Special Issue, Sept.-Oct. 01, pp. 7-58.

application-specific SOC multiprocessors, Guest Editors' Introduction, W. Wolf et al., Sept.-Oct. 01, p. 7.

defect-oriented diagnosis for very deep-submicron systems, Special Issue, Jan.-Feb. 01, pp. 8-61.

defect-oriented diagnosis for very deep-submicron systems, Guest Editors' Introduction, F. Lombardi et al., Jan.-Feb. 01, pp. 8-9.

dynamic power management of electronic systems, Special Issue, Mar.-Apr. 01, pp. 6-74.

dynamic power management of electronic systems, Guest Editor's Introduction, E. Macii et al., Mar.-Apr. 01, pp. 6-9.

formal verification of commercial ICs, Special Issue, July-Aug. 01, pp. 4-45.

formal verification of commercial ICs, Guest Editor's Introduction, C. Pixley, July-Aug. 01, pp. 4-5.

large embedded memories, Special Issue, May-June 01, pp. 3-82.

large embedded memories, Guest Editors' Introduction, R. Rajsuman et al., May-June 01, pp. 3-4.

roadmaps and visions for design and test, Special Issue, Nov.-Dec. 01, pp. 4-54.

roadmaps and visions for design and test, Guest Editors' Introduction, A. Kahng et al., pp. 4-5.

test trade-offs, issues covered at 2001 International Test Conference (ITC), Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

test trade-offs take center stage at ITC, Special Issue, Sept.-Oct. 01, pp. 59-99.

test trade-offs take center stage at ITC, Guest Editors' Introduction, T. Ambler et al., Sept.-Oct. 01, p. 59.

Specification languages

SOC specification and modeling using C++, challenges and opportunities, Roundtable, May-June 01, pp. 115-123.

Specification languages,
see Hardware description languages.
SPICE

mixed-signal circuits, verification test system modeling, D.S.S. Bello et al., Jan.-Feb. 01, pp. 63-71.

SRAM chips

online/offline BIST in IP-core design, A. Benso et al., Sept.-Oct. 01, pp. 92-99.

Storage capacity

huge storage capacity, Y. Zorian, From the EIC, May-June 01, p. 1.

Storage management,
see Buffer storage.
Submicron defects

defects in deep-submicron tests, R.C. Aitken, The Last Byte, Jan.-Feb. 01, p. 96.

Subscriber loops,
see Radio access networks.
Switching circuits,
see Logic circuits.
Systems on chips

adding reconfigurable logic to SOC designs, Roundtable, July-Aug. 01, pp. 65-71.

application-specific SOC multiprocessors, Special Issue, Sept.-Oct. 01, pp. 7-58.

application-specific SOC multiprocessors, Guest Editors' Introduction, W. Wolf et al., Sept.-Oct. 01, p. 7.

automated design of SOCs using cores, R.A. Bergamaschi et al., Sept.-Oct. 01, pp. 32-45.

Colif, design representation for application-specific multiprocessor SOCs, W.O. Cesario et al., Sept.-Oct. 01, pp. 8-20.

energy-aware runtime scheduling for embedded multiprocessor SOCs, P. Yang et al., Sept.-Oct. 01, pp. 46-58.

optimizing SOC design and resource optimization for testing complex SOCs, Y. Zorian, From the EIC, Sept.-Oct. 01, p. 1.

SOC testability using LSSD scan structures, K. Zarrineh et al., May-June 01, pp. 83-97.

test resource partitioning for SOCs, A. Chandra et al., Sept.-Oct. 01, pp. 80-91.

SOCs, embedded memory, Perspectives, A. Shubat, May-June 01, pp. 5-6.

Viper, multiprocessor SOC for advanced set-top box and digital TV systems, S. Dutta et al., Sept.-Oct. 01, pp. 21-31.

T
Technology

welcome to 2001, S. Davidson, The Last Byte, Mar.-Apr. 01, p. 112.

Telecommunication,
see Data communication.
Television receivers

Viper, multiprocessor SOC for advanced set-top box and digital TV systems, S. Dutta et al., Sept.-Oct. 01, pp. 21-31.

Test equipment,
see Automatic test equipment.
Test strategies

strategies for low-cost test, R. Kapur et al., Nov.-Dec. 01, pp. 47-54.

test strategies and marriage partners, T. Ambler, The Last Byte, Sept.-Oct. 01, p. 128.

Testing

industry and university test research collaboration, Roundtable, Mar.-Apr. 01, pp. 98-105.

Testing,
see Boundary scan testing, Logic testing, Program testing.
Theorem proving

formal verification methodology for microprocessor design, R.B. Jones et al., July-Aug. 01, pp. 16-25.

U
Universities

industry and university test research collaboration, Roundtable, Mar.-Apr. 01, pp. 98-105.

V
Verification,
see Formal verification
VHDL

VHDL standards, P.J. Ashenden, Standards, Sept.-Oct. 01, pp. 122-123.

VLSI

AFM for deep submicron failure analysis, J.-C. Lo et al., Jan.-Feb. 01, pp. 10-18.

current-based testing for deep-submicron VLSIs, M. Sachdev, Mar.-Apr. 01, pp. 76-84.

very low cost testers, J. Bedsole et al., Sept.-Oct. 01, pp. 60-69.

Voltage control

intra-task voltage scheduling for low-energy hard real-time applications, D. Shin et al., Mar.-Apr. 01, pp. 20-30.

W
Waveform analysis

IDD waveform analysis for fault detection and location, K. Muhammad et al., Jan.-Feb. 01, pp. 42-49.

23 ms
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