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A Mixed-Signal Design Roadmap
November/December 2001 (vol. 18 no. 6)
pp. 34-46
ASCII Text
x 
 
Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt, "A Mixed-Signal Design Roadmap," IEEE Design & Test of Computers, vol. 18, no. 6, pp. 34-46, November/December, 2001.
 
 
BibTex
x
 
@article{ 10.1109/54.970422,
author = {Ralf Brederlow and Werner Weber and Joseph Sauerer and Stéphane Donnay and Piet Wambacq and Maarten Vertregt},
title = {A Mixed-Signal Design Roadmap},
journal ={IEEE Design & Test of Computers},
volume = {18},
number = {6},
issn = {0740-7475},
year = {2001},
pages = {34-46},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.970422},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - A Mixed-Signal Design Roadmap
IS - 6
SN - 0740-7475
SP34
EP46
EPD - 34-46
A1 - Ralf Brederlow,
A1 - Werner Weber,
A1 - Joseph Sauerer,
A1 - Stéphane Donnay,
A1 - Piet Wambacq,
A1 - Maarten Vertregt,
PY - 2001
VL - 18
JA - IEEE Design & Test of Computers
ER -
 

This roadmap for the 2001 International Technology Roadmap for Semiconductors uses performance figures of merit (FoMs) derived from basic circuits critical to mixed-signal design performance. Extrapolations from the FoMs to future performance values establish the device parameters necessary for design progress.

Citation:
Ralf Brederlow, Werner Weber, Joseph Sauerer, Stéphane Donnay, Piet Wambacq, Maarten Vertregt, "A Mixed-Signal Design Roadmap," IEEE Design & Test of Computers, vol. 18, no. 6, pp. 34-46, Nov.-Dec. 2001, doi:10.1109/54.970422
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