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Issue No.05 - September/October (2001 vol.18)
pp: 92-99
ABSTRACT
<p>This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints.</p>
CITATION
Silvia Chiusano, Giorgio Di Natale, Alfredo Benso, Monica Lobetti Bondoni, "Online and Offline BIST in IP-Core Design", IEEE Design & Test of Computers, vol.18, no. 5, pp. 92-99, September/October 2001, doi:10.1109/54.953276
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