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Online and Offline BIST in IP-Core Design
September/October 2001 (vol. 18 no. 5)
pp. 92-99

This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraints.

Citation:
Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bondoni, "Online and Offline BIST in IP-Core Design," IEEE Design & Test of Computers, vol. 18, no. 5, pp. 92-99, Sept.-Oct. 2001, doi:10.1109/54.953276
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