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Automating the Design of SOCs Using Cores
September/October 2001 (vol. 18 no. 5)
pp. 32-45

Assembling a system on a chip using IP blocks is an error-prone, labor-intensive, and time-consuming process. Emerging high-level tools can help by automating many of the design tasks.

Citation:
Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Ronoldo Wagner, Colleen Fellenz, Michael Muhlada, William R. Lee, Foster White, Jean-Marc Daveau, "Automating the Design of SOCs Using Cores," IEEE Design & Test of Computers, vol. 18, no. 5, pp. 32-45, Sept.-Oct. 2001, doi:10.1109/54.953270
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