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Practical Formal Verification in Microprocessor Design
July/August 2001 (vol. 18 no. 4)
pp. 16-25
ASCII Text
x 
 
Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham, "Practical Formal Verification in Microprocessor Design," IEEE Design & Test of Computers, vol. 18, no. 4, pp. 16-25, July/August, 2001.
 
 
BibTex
x
 
@article{ 10.1109/54.936245,
author = {Robert B. Jones and John W. O'Leary and Carl-Johan H. Seger and Mark D. Aagaard and Thomas F. Melham},
title = {Practical Formal Verification in Microprocessor Design},
journal ={IEEE Design & Test of Computers},
volume = {18},
number = {4},
issn = {0740-7475},
year = {2001},
pages = {16-25},
doi = {http://doi.ieeecomputersociety.org/10.1109/54.936245},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Practical Formal Verification in Microprocessor Design
IS - 4
SN - 0740-7475
SP16
EP25
EPD - 16-25
A1 - Robert B. Jones,
A1 - John W. O'Leary,
A1 - Carl-Johan H. Seger,
A1 - Mark D. Aagaard,
A1 - Thomas F. Melham,
PY - 2001
VL - 18
JA - IEEE Design & Test of Computers
ER -
 
Practical application of formal methods requires more than advanced technology and tools; it requires an appropriate methodology. A verification methodology for data-path-dominated hardware combines model checking and theorem proving in a customizable framework. This methodology has been effective in large-scale industrial trials, including verification of an IEEE-compliant floating-point adder.
Citation:
Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham, "Practical Formal Verification in Microprocessor Design," IEEE Design & Test of Computers, vol. 18, no. 4, pp. 16-25, July-Aug. 2001, doi:10.1109/54.936245
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