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Design and Test of Large Embedded Memories: An Overview
May/June 2001 (vol. 18 no. 3)
pp. 16-27
Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair.
Citation:
Rochit Rajsuman, "Design and Test of Large Embedded Memories: An Overview," IEEE Design & Test of Computers, vol. 18, no. 3, pp. 16-27, May-June 2001, doi:10.1109/54.922800
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