Issue No.04 - October-December (2000 vol.17)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.895003
Power in processing cores (embedded processors, DSPs) is primarily consumed in the datapath part which consists of high activity functional modules. In this paper, we propose low power/energy BIST schemes for datapath architectures built around the most common combinations of multipliers, adders, ALUs and shifters. The proposed BIST schemes are based on deterministic regular test sets. Different alternatives are proposed depending on whether the target is low total energy dissipation during an entire BIST session or low power dissipation (i.e. average energy dissipation between successive test vectors). The proposed BIST schemes are more efficient than pseudorandom BIST in terms of power/energy consumption for the same high fault coverage targets as shown by a comprehensive set of experiments performed using commercial power analysis tools. This fact is due to much lower circuit activity of the proposed deterministic BIST schemes compared to the circuit activity of classical pseudorandom BIST schemes.
Nektarios Kranitis, Dimitris Gizopoulos, Antonis Paschalis, Mihalis Psarakis, Yervant Zorian, "Power-/Energy Efficient BIST Schemes for Processor Data Paths", IEEE Design & Test of Computers, vol.17, no. 4, pp. 15-28, October-December 2000, doi:10.1109/54.895003