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RT-Level ITC'99 Benchmarks and First ATPG Results
July-September 2000 (vol. 17 no. 3)
pp. 44-53

New design flows require reducing work at the gate level and perfoming most activities before the synthesis step, including evaluatation of testability of circuits. We propose a suite of RT-level benchmarks that help improve research in high-level ATPG tools. First results on the benchmarks obtained with our prototype tool show the feasibility of the approach.

Citation:
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, "RT-Level ITC'99 Benchmarks and First ATPG Results," IEEE Design & Test of Computers, vol. 17, no. 3, pp. 44-53, July-Sept. 2000, doi:10.1109/54.867894
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