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Inserting Scan at the Behavioral Level
July-September 2000 (vol. 17 no. 3)
pp. 34-42

This article presents a method for inserting test logic at the behavioral level of a VHDL design description. The method is easy to use, and in most cases it requires lower area overhead than classical scan insertion methods.

Citation:
Chouki Aktouf, Hérvé Fleury, Chantal Robach, "Inserting Scan at the Behavioral Level," IEEE Design & Test of Computers, vol. 17, no. 3, pp. 34-42, July-Sept. 2000, doi:10.1109/54.867892
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