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Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability
April-June 2000 (vol. 17 no. 2)
pp. 94-99
| ASCII Text | x | ||
| Dilip Bhavsar, "Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability," IEEE Design & Test of Computers, vol. 17, no. 2, pp. 94-99, April-June, 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/54.844338, author = {Dilip Bhavsar}, title = {Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability}, journal ={IEEE Design & Test of Computers}, volume = {17}, number = {2}, issn = {0740-7475}, year = {2000}, pages = {94-99}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.844338}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability IS - 2 SN - 0740-7475 SP94 EP99 EPD - 94-99 A1 - Dilip Bhavsar, PY - 2000 VL - 17 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.844338
This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.
Citation:
Dilip Bhavsar, "Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability," IEEE Design & Test of Computers, vol. 17, no. 2, pp. 94-99, April-June 2000, doi:10.1109/54.844338
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