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Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability
April-June 2000 (vol. 17 no. 2)
pp. 94-99

This strategy enhances the test port to let it operate with two clocks. One is used while accessing IEEE 1149.1-compliant features, the other while accessing chip manufacturing test features.

Citation:
Dilip Bhavsar, "Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability," IEEE Design & Test of Computers, vol. 17, no. 2, pp. 94-99, April-June 2000, doi:10.1109/54.844338
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