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Issue No.04 - October-December (1999 vol.16)
pp: 28-38
ABSTRACT
Many difficulties that can prevent the introduction of the next generation of large-volume chips embedding MEMS are strongly related to testing. The intimate linkage of form and function in MEMS parts makes unavoidable the integration of design and test from the very beginning, building models that can take fault injection into account, and using them during fault simulation and test generation. This article illustrates this problem for chips that use bulk and surface silicon micromachining for the fabrication of MEMS parts. Micromachining defects are targeted because they are unique to the MEMS components and need to be incorporated in a test strategy for the overall chip. We use suspended thermal MEMS and electrostatic micromechanical resonators as representative test vehicles. As for purely microelectronic chips, the adoption of fault-based or defect-oriented approaches can help the validation of complex systems and the generation of structured tests, in part alleviating high testing costs in this next generation of chips.
INDEX TERMS
MEMS, IC Defects, Failure Mechanisms, Fault Modeling, HDLs.
CITATION
Salvador Mir, Benoit Charlot, "On the Integration of Design and Test for Chips Embedding MEMS", IEEE Design & Test of Computers, vol.16, no. 4, pp. 28-38, October-December 1999, doi:10.1109/54.808204
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