Issue No.04 - October-December (1999 vol.16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.808200
The advent of monolithic integration of mechanical structures with electronics has ushered in an era in which microchips can sense and act as well as compute and communicate. The complex device, component, and system design issues involving such integrated chips require the development of new CAD representations, methodologies, and tools. In this article, we present a suite of tools that simultaneously considers the mechanical and electromechanical nature of such microsystems versus traditional electronics. These tools are based on a design methodology that partitions the micromechanical and electromechanical components in a hierarchical fashion into low-level reusable elements. This mixed-domain circuit representation is combined with Kirchhoffian network theory for an integrated microsystem simulation environment. Behavioral models from this hierarchical representation are combined with optimization into a tool that generates microstructure layouts meeting specified performance criteria. A feature-recognition-based extractor translates layout geometry into the mixed-domain circuit representation, enabling layout verification. Models that integrate the effects of process contaminations on a microstructure form the basis of a MEMS testing methodology.
MEMS, hierarchical circuit representation, nodal simulation, synthesis, extraction, testing methodology
Tamal Mukherjee, Gary K. Fedder, R.D. (Shawn) Blanton, "Hierarchical Design and Test of Integrated Microsystems", IEEE Design & Test of Computers, vol.16, no. 4, pp. 18-27, October-December 1999, doi:10.1109/54.808200