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Fault-Secure Parity Prediction Booth Multipliers
July-September 1999 (vol. 16 no. 3)
pp. 90-101
Parity-prediction arithmetic operator schemes are compatible with data paths and memory systems checked by parity codes. The drawback of these schemes is that they may not be fault secure for single faults, since they propagate to multiple output errors undetectable by the parity code. In a recent work we proposed a theory for achieving fault-secure design for parity-prediction multipliers and dividers. We did not consider the case of Booth multipliers using operand recoding. Since Booth multipliers are among the most popular, in this article we derive the parity-prediction logic for Booth multipliers and propose a fault-secure implementation for this scheme. Due to the particular structure of these multipliers, parity prediction is not as straightforward as in multipliers with non-recoded operands. Also, fault-secure design requires a specific solution to cope with even-cell fan-out signals.
Index Terms:
self-checking circuits, fault secure circuits, parity prediction, booth multipliers.
Citation:
Michael Nicolaidis, Ricardo O. Duarte, "Fault-Secure Parity Prediction Booth Multipliers," IEEE Design & Test of Computers, vol. 16, no. 3, pp. 90-101, July-Sept. 1999, doi:10.1109/54.785842
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