Issue No.03 - July-September (1999 vol.16)
Published by the IEEE Computer Society
Organizers of the 1999 International Test Conference decided to focus this year's meetings on the test and the product life cycle. The meetings highlight and demonstrate the pervasiveness of testability design throughout all stages of test: from the chip, board, and system levels through to field service.
The implications of chip-level testability beyond chip test can be immense in terms of easing board-level test. "Ease" can be construed to mean many things, including
• time taken to create the test patterns and protocols
• numbers of test patterns required
• test-application runtime
• achieving a sufficiently-high fault coverage
• minimizing the cost of test
Ultimately, quality and cost are the major arbiters. Once we take quality and cost into consideration, we can move beyond board-level test and make similar extrapolations to system test and field test. This was demonstrated beautifully in the mythical, but oft-quoted, rule-of-tens. 1
Figure 1 shows the advance in the cost of test with successive stages of test. Say that the cost to detect a fault at chip-level testing is $1. After that component is integrated into a board, it would cost 10 times as much to detect the same fault. It would cost 10 times more to detect the same fault when the board that the chip is on is integrated into a system, and so on. In practice, the cost increase is not "times 10," but the increase does rise nonlinearly as we progress from chip to board to system to field service.
Thus, an understanding of the benefits of testability design at all levels of integration is of paramount interest, ultimately, to everyone (or should be!).
Testability has other, but somewhat less tangible benefits, in the form of improving time to market. Once we improve diagnosability by adding testability-related features to the design, design debugging becomes that much easier, and quicker. Time to market is a primary concern in the electronics business today and can mean the difference between product success and failure. See Figure 2.
It is probably true that much of the chip design business does not take into account the problems that are likely to be encountered by board-level testability requirements and subsequent levels of product hierarchy. This is not too unusual—if you are a merchant chip vendor, your requirement is to produce chips, at an affordable cost. It is true that many testability features that can be added to devices will add to the cost of that device. (The literature provides wide discussions of chip test economics; no doubt, it will continue to be debated for some time to come. 2) People have reported many times that board developers have not been too pleased at paying more for chip-level testability enhancements. Boundary scan is a well-known chip feature that is aimed specifically at board-level testability. 3
The use and application of boundary scan does require the complicity of the chip designers, and will add to chip cost. The use and integration of boundary scan has not been as prolific as had been hoped. However, recent excursions into in-system programming coupled with a continuing decrease in physical access for nails is driving boundary scan into mainstream adoption.
Clearly, the understanding by the industry of the testability requirements of the different levels of the hierarchy is not as it should be.
We hope this issue of IEEE Design & Test of Computers will help redress that imbalance with a set of five articles submitted in response to a call for papers.
Jon Turino, who has been in the test industry for many years, offers us his perspective on the time-to-market impact of design for testability at the chip level, with examples based upon his experiences.
Bernard Sutton, who has been in the board test arena for most of his career, looks at the board test issue from a broad perspective and identifies the need for different test strategies for different boards.
Mike Wondolowski and his colleagues look specifically at boundary scan test and show how it opens up reuse of chip design-for-testability features, such as scan and BIST, throughout the life cycle of the product. This assists board, system, and field-service diagnostics.
Bertram Weber presents his experiences in system test of a communication switch. This is a specific example of the system test requirements applied to a particular product type. His perspectives show how the complexities of system test can be approached.
Susana Stoica introduces us to Robust Test Methodology as applied to software test. This is essential when we approach system-level test, where the total package of electronics and software finally come together.
Finally, please remember the theme of the 1999 ITC Conference, Test and the Product Life Cycle. There will be much more material at the conference to support and extend what we've been able to put together for this special issue of Design and Test.
Tony Ambler teaches at the University of Texas at Austin, where he holds the B.N. Gafford Endowed Chair in Electrical Engineering. Previously, he held the IMS Chair of Test Technology in the Department of Electrical Engineering and Electronics at Brunel University, UK. Involved in test, design for testability, and test economics for many years, he has cofounded a series of international workshops on test economics. He has copresented the test economics tutorial at the International Test Conference, served as program chair and general chair of the International Conference on Computer Design, and as general chair of the European Design and Test Conference. He cochairs the IEEE Computer Society's Test Technology Technical Committee TAC on Test Economics, and serves on the editorial boards of IEEE D&T and the Journal of Electronic Test: Theory and Applications. Ambler received his BSc, MSc, and PhD from the University of Manchester Institute of Science and Technology, UK.
Ben Bennetts is an independent design-for-test consultant, advising and teaching on product-life-cycle DFT strategies. Previously, he has worked for LogicVision, Synopsys, GenRad, and Cirrus Computers. He has also been a free-lance consultant and lecturer on DFT topics. During that time, he was a member of JTAG, the organization that created the IEEE 1149.1 Boundary-Scan standard. Bennetts received a PhD in computer science from Southampton University. He has published over 90 papers and three books on test and DFT subjects. He is a senior member of the IEEE, a fellow of the IEE, and a member of the Computer Society.