Issue No.02 - April-June (1999 vol.16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.765206
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field- Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PLA-like blocks. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The proposed Hybrid FPGA is evaluated by technology mapping a set of circuits into the new architecture and estimating the total chip area needed and the depth for each circuit, compared to the area and depth that would be required if only LUTs were available. Our results indicate that on average LUT-based FPGAs need 78% more area than the Hybrid, while providing roughly the same depth for the circuits. Also, we show that it is possible to optimize the circuits for depth, such that the critical path of the circuits implemented in the new architecture is significantly shorter than the critical path when they are mapped to LUT-based FPGAs.
Alireza Kaviani, "The Hybrid Field-Programmable Architecture", IEEE Design & Test of Computers, vol.16, no. 2, pp. 74-83, April-June 1999, doi:10.1109/54.765206