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Design Verification of FPGA Implementations
April-June 1999 (vol. 16 no. 2)
pp. 66-73
This paper presents an approach to design verification of digital circuits implemented with field programmable gate arrays (FPGAs). This approach is based on the criterion of an equivalent class to establish the equivalence between two circuits and designs. This objective is achieved using simulation and automatic test pattern generation (ATPG) and it exploits similarities among designs to assess logical equivalence in a fast and reliable manner. Initially, design information is used for establishing the location of the nodes (internal as well as primary inputs and outputs) from which dynamic signatures are then obtained using simulation. Nodes with the same signature make up a so-called equivalent class, which is updated using the simulation results as well as the outcome of the verification process. A dynamic modification of the signatures and an appropriate data structure for taking into account the outcome of each simulation run, are presented. The complexity of the proposed approach is O(n) ATPG time (with circuit simulation) or O (nk)ATPG time (without circuit simulation), where n is the number of nodes in the circuit and k is the maximum size of the equivalent class (usually a constant and k ! n). This compares favourably with [1] which has a complexity of O (n2)ATPG time. \par It is shown that equivalent nodes must remain in the same equivalent class, else equivalence in design is not possible. The proposed approach has been evaluated using industrial circuits and has been shown to yield excellent results for verifying circuits implemented using various FPGA families by Actel.
Index Terms:
Verification, FPGA, ATPG, Equivalent Classes, Miter.
Citation:
Xiao-Tao Chen, Wei-Kang Huang, Nohpill Park, Fred J. Meyer, Fabrizio Lombardi, "Design Verification of FPGA Implementations," IEEE Design & Test of Computers, vol. 16, no. 2, pp. 66-73, April-June 1999, doi:10.1109/54.765205
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