Issue No.02 - April-June (1999 vol.16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.765204
In this article two IDDQ testable PLA configurations are proposed. In these configurations adjacent precharge lines (and adjacent evaluation lines) are precharged (evaluated) to complementary logic levels. Owing to this DfT technique, all likely bridging faults in PLAs are tested efficiently by IDDQ tests. Such a test is largely independent of the function implemented in a PLA. The performance impact of these configurations are also examined.
IDDQ testing, PLA design, PLA performance
Manoj Sachdev, Hans Kerkhoff, "Configurations for IDDQ-Testable PLAs", IEEE Design & Test of Computers, vol.16, no. 2, pp. 58-65, April-June 1999, doi:10.1109/54.765204