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Issue No.01 - January-March (1999 vol.16)
pp: 59-70
ABSTRACT
With the advent of deep-submicron VLSI technology, ASIC vendors are turning toward the single-chip system solution which integrates cores from various sources. Memory is one of the most universal cores-almost all system chips contain some type of embedded memory. Embedded SRAM's have been widely used, since by merging memory with logic, data bandwidth can be increased and hardware cost can be reduced. Now, with multimillion-gate designs that are pad-limited, we can see why embedded DRAM is also becoming an attractive core to them. With the clear trend that embedded DRAM will play an important role in the IC market over the next few years, their testing is becoming an industry-wide concern. Built-in self-test (BIST) is widely considered to be the best way for functional testing of embedded DRAM's. In this paper, we propose a programmable embedded DRAM BIST scheme which supports various test modes using a simple controller. An EDO DRAM is used as an example to delineate our BIST design and implementation. A novel memory fault simulator also has been implemented and used to analyze the fault coverage of the test algorithms for our BIST design. Our analysis shows that, with the March C- algorithm, the BIST overhead is less than 1.3% for a 1Mb DRAM, and it drops to below 0.3% for a 16Mb DRAM. Also, since the proposed BIST design is programmable, it can easily be applied to other DRAM types.
INDEX TERMS
DRAM, embedded memory, BIST, EDO DRAM
CITATION
Chih-Tsun Huang, Jing-Reng Huang, Chi-Feng Wu, Cheng-Wen Wu, Tsin-Yuan Chang, "A Programmable BIST Core for Embedded DRAM", IEEE Design & Test of Computers, vol.16, no. 1, pp. 59-70, January-March 1999, doi:10.1109/54.748806
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