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Universal Test Interface for Embedded-DRAM Testing
January-March 1999 (vol. 16 no. 1)
pp. 53-58
| ASCII Text | x | ||
| Shinji Miyano, Katsuhiko Sato, Kenji Numata, "Universal Test Interface for Embedded-DRAM Testing," IEEE Design & Test of Computers, vol. 16, no. 1, pp. 53-58, January-March, 1999. | |||
| BibTex | x | ||
| @article{ 10.1109/54.748805, author = {Shinji Miyano and Katsuhiko Sato and Kenji Numata}, title = {Universal Test Interface for Embedded-DRAM Testing}, journal ={IEEE Design & Test of Computers}, volume = {16}, number = {1}, issn = {0740-7475}, year = {1999}, pages = {53-58}, doi = {http://doi.ieeecomputersociety.org/10.1109/54.748805}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - MGZN JO - IEEE Design & Test of Computers TI - Universal Test Interface for Embedded-DRAM Testing IS - 1 SN - 0740-7475 SP53 EP58 EPD - 53-58 A1 - Shinji Miyano, A1 - Katsuhiko Sato, A1 - Kenji Numata, PY - 1999 KW - Embedded DRAM KW - Direct Access Mode KW - Universal Test Interface KW - BIST VL - 16 JA - IEEE Design & Test of Computers ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.748805
This paper describes circuitry for facilitating the test of embedded DRAM macro whose configuration can be easily changed (reconfigurable macro). It is difficult to use conventional direct access mode circuitry, because the configuration of embedded DRAMs on a chip is varied for each product, and therefor the test circuitry should be customized for each product. The proposed test circuits implemented in the macro provide a Universal Test Interface regardless of the DRAM configuration and the number of macros on a chip.
Index Terms:
Embedded DRAM, Direct Access Mode, Universal Test Interface, BIST
Citation:
Shinji Miyano, Katsuhiko Sato, Kenji Numata, "Universal Test Interface for Embedded-DRAM Testing," IEEE Design & Test of Computers, vol. 16, no. 1, pp. 53-58, Jan.-March 1999, doi:10.1109/54.748805
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