Issue No.01 - January-March (1999 vol.16)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.748804
Two approaches for next generation memory bus architecture, SLDRAM and Direct Rambus, are evaluated using a commercial analog circuit simulator to model transmission line behavior. Sources of error that degrade signal integrity, such as pulse amplitude attenuation, pulse width dependent skew or intersymbol interference, crosstalk, and clock to data skew are quantified to determine the operating margin of the two alternatives. Bus power dissipation is also considered. A fully loaded SLDRAM configuration is shown to have more timing margin than Direct Rambus.
DRAM, SLDRAM, Direct Rambus, memory design
Bruce Millar, "Two High-Bandwidth Memory Bus Structures", IEEE Design & Test of Computers, vol.16, no. 1, pp. 42-52, January-March 1999, doi:10.1109/54.748804