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Fault Models and Tests for a 2-Bit-per-Cell MLDRAM
January-March 1999 (vol. 16 no. 1)
pp. 22-31
This article presents a fault model and testing strategies for a 2-bit per cell dynamic random-access memory (DRAM). Multilevel DRAM technology may become an important way of increasing the storage density of semiconductor memory for a given process and minimum feature size. The multilevel DRAM that we consider re-uses many proven elements from a conventional 1-bit per cell DRAM cell array. From a list of reported DRAM physical defects we develop a fault model using both manual analysis and analog simulation. Several alternative testing strategies are proposed that make different trade-offs between testing cost and possible design for testability enhancements.
Index Terms:
dynamic random-access memory, DRAM, multilevel DRAM, fault modeling, memory testing.
Citation:
Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, "Fault Models and Tests for a 2-Bit-per-Cell MLDRAM," IEEE Design & Test of Computers, vol. 16, no. 1, pp. 22-31, Jan.-March 1999, doi:10.1109/54.748802
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