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Issue No.04 - October-December (1998 vol.15)
pp: 66-74
ABSTRACT
<p>Hardware and information redundancy are two among the most widespread strategies for designing circuits with concurrent detection properties. These design approaches guarantee the desired property by partitioning the set of output configurations that a device may produce into two classes: those produced in a fault free situation and those caused by at least a fault within either the network or the checker circuit. This functional property allows the coverage of all faults that produce an error on the outputs such that the generated configuration does not belong to the fault-free output set. Whenever this does not happen, the fault is not detected, either causing no error (fault redundant with respect to the input configuration) or producing a fault-free output different from the correct one (critical situation). To achieve a complete fault coverage a constrained synthesis must support the functional encoding, guaranteeing that each fault produces only detectable errors. If there is a lack, either at functional encoding level or at the structural synthesis level, due to costs and complexity, the device will only be partially self-checking.</p> <p>This paper proposes an approach, supported by a tool the authors developed, for fault analysis and simulation of networks designed to have concurrent detection properties, either partially or completely, to characterize all faults that may affect the device, determining the coverage, when incomplete, extracting test vectors and other parameters for evaluating the quality of the device. The methodology may be used both during the realization of the device, supporting network realization to fulfill the functional encoding, and a-posteriori, when the device is partially o totally self-checking, for an evaluation and possible comparison with different solutions.</p>
INDEX TERMS
Concurrent Error Detection, Fault Observability, Weight, Fault Classification, Test Vectors
CITATION
Fabio Salice, Cristiana Bolchini, "Fault Analysis for Networks with Concurrent Error Detection", IEEE Design & Test of Computers, vol.15, no. 4, pp. 66-74, October-December 1998, doi:10.1109/54.735929
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