Issue No.04 - October-December (1998 vol.15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.735926
This paper presents a novel concept for concurrently checking the correctness of signals of clock distribution networks of synchronous systems. A VLSI circuitry is then proposed that, based on such a concept, performs the concurrent checking of such signals with respect to permanent and temporary (i.e., transient and intermittent) faults (permanently or temporary) changing their waveforms with respect to those expected in the fault-free case. Such a circuitry is in turn self-checking with respect to its possible permanent, as well as temporary, internal, realistic faults.
Concurrent checking, clock signals, temporary faults, self-checking circuits
Michele Favalli, Bruno Riccò, "Concurrent Checking of Clock Signal Correctness", IEEE Design & Test of Computers, vol.15, no. 4, pp. 42-48, October-December 1998, doi:10.1109/54.735926