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Online BIST for Embedded Systems
October-December 1998 (vol. 15 no. 4)
pp. 17-24
We survey online testing techniques in embedded systems and evaluate them based on the following parameters: error coverage, error latency, space redundancy, and time redundancy. We then discuss online BIST methods that provide full error coverage, bounded error latency, low space and time redundancy, and impose no redesign constraints on the circuit under test. Finally, we discuss a recently designed commercial microprocessor for critical applications that incorporate most of the methods considered.
Index Terms:
Online testing, BIST, embedded systems, fault tolerance, fail-safe design.
Citation:
Hussain Al-Asaad, Brian T. Murray, John P. Hayes, "Online BIST for Embedded Systems," IEEE Design & Test of Computers, vol. 15, no. 4, pp. 17-24, Oct.-Dec. 1998, doi:10.1109/54.735923
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