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Issue No.03 - July-September (1998 vol.15)
pp: 90-97
ABSTRACT
Time to market demands for the PowerPC 750 microprocessor require new test strategy approaches to improving the product test quality, reliability, and debug process. The total time to market includes not just the design cycle time to the initial tapeout, but also the productization time. Strong debug support and silicon verification are key to reducing the time to market. A test suite with high test effectiveness must be prepared before initial parts are available to minimize debug efforts on defective silicon. The implementation of the design for test and debug features also must be balanced with requirements for processor performance. The PowerPC 750 test strategy includes enhanced or new design for test features and improved test generation and debug processes
INDEX TERMS
Microprocessor Test, Design for Test, LSSD, Silicon Verification
CITATION
Carol Pyron, Javier Prado, James Golab, "Test Strategy for the PowerPC 750 Microprocessor", IEEE Design & Test of Computers, vol.15, no. 3, pp. 90-97, July-September 1998, doi:10.1109/54.706039
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