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Design of Cache Test Hardware on the HP PA8500
July-September 1998 (vol. 15 no. 3)
pp. 58-63

The PA7300 was the first PA-RISC microprocessor to incorporate an on-chip cache. To test its 128-Kbyte memory, test hardware was included consisting of an input register, an output MISR, an LFSR address source, and a state machine. The state machine was capable of executing a predefined march test with a fixed address sequence and programmable data pattern. The successes achieved on the PA7300 using this strategy, combined with some of its shortcomings, have lead to the development of a memory test subsystem on Hewlett Packard's next microprocessor, the PA8500.

This article describes the memory test hardware on the PA8500, beginning with the requirements that motivated the design. An explanation of the cache architecture is given, and followed by a description of the blocks that make up the memory test subsystem. The final section presents an example that shows how the subsystem can be used to test the memory.

Index Terms:
Memory test hardware, PA8500, cache architecture, cache design
Citation:
Jeff Brauch, Jay Fleischman, "Design of Cache Test Hardware on the HP PA8500," IEEE Design & Test of Computers, vol. 15, no. 3, pp. 58-63, July-Sept. 1998, doi:10.1109/54.706034
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