Issue No.03 - July-September (1998 vol.15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.706032
Advanced packaging technologies such as 3D chip stacking, multichip modules (MCMs), and 3D stacks of MCMs provide opportunities for significant reductions in system mass, volume and power. They also pose major testing challenges that need to be resolved before they are used in mainstream designs. Among these challenges, the problems of achieving acceptable assembly yields and meeting product quality requirements through appropriate test methodologies are very critical. Both these problems can be significantly alleviated by adopting testing approaches which guarantee the integrity and performance of the underlying packaging technologies. In this article, we propose test methodologies for a 3D stack of MCMs used by the flight computer of the NASA New Millennium Program (NMP) Deep-Space mission spacecraft. The test methodologies are based on the IEEE 1149.1 Boundary Scan Standard architecture. Special test chips are used for reliable test and diagnosis of the 3D MCM stack-based flight computer architecture. Also, the range of test options available are evaluated and ranked with respect to test time, test hardware, number of test lines, and test reliability. The test hardware has been fabricated and is scheduled to fly in space in the near future.
Packaging technology, ICs, multichip modules, 3D MCMs, test methodology
Koppol Sasidhar, Leon Alkalai, Abhijit Chatterjee, "Testing NASA's 3D-Stack MCM Space Flight Computer", IEEE Design & Test of Computers, vol.15, no. 3, pp. 44-55, July-September 1998, doi:10.1109/54.706032