Issue No.03 - July-September (1998 vol.15)
Published by the IEEE Computer Society
Sometimes our experience of technological change in the electronics industry seems similar to our view of a forest from a speeding train—a blur of trees with little perspective on the forest's overall pattern. This is particularly true with respect to advances in electronic packaging. IC technology has been following an evolutionary path of CMOS device and system scaling. Meanwhile, packaging technologists have had to develop many innovative approaches to overcome ever-greater packaging-related bottlenecks as IC density and performance have increased. Alternatives abound—from single-chip modules (SCMs) to multichip modules (MCMs), from peripheral to area bonding, from ceramic packages to chip-scale packaging (CSP), from quad flat packs (QFPs) to ball grid arrays (BGAs). To make things more complex, many of these alternatives present a spectrum of choices. For example, MCMs may be "flavored" C, D, or L—ceramic, deposited, or laminated—with several processing and material choices within each category.
These diverse packaging technologies strongly impact the feasibility and performance of systems that incorporate them. For a system designer, evaluating these alternatives may be problematic due to the complexity of those systems and the difficulty of developing expertise in a rapidly changing set of technologies. To make matters worse, there may be subtle dependencies between technology choices and system design specifications and constraints. Technology and system architecture decisions made early in the design process may have cost and performance implications that don't appear until much later.
This special issue focuses on the need to understand these issues early in the design process. The choice of modeling parameters is very important for an accurate and realistic study of future costs. In the case of economic models, simple is not necessarily best because the impact of seemingly minor decisions can be highly significant.
The Sandborn and Vertal article describes the complex interactions of the diverse factors that affect system cost and performance metrics. Their virtual prototyping methodology and tool allow developers to consider packaging trade-offs within the system design methodology, prior to large investments in design. They present case studies that illustrate the analysis process and typical outcomes.
A complementary article by Scheffler and his colleagues focuses on several approaches to the cost-modeling problem underlying trade-off analysis. It introduces the Modular Optimization Environment and an associated graphical user interface, which simplify and standardize the modeling process. The authors illustrate their methodology with a comparison of a system designed with a "standard" MCM-D substrate and one designed with an "active" substrate that incorporates transistors as switching elements. It turns out that because this more expensive substrate facilitates early testing, the overall system cost may be less. The lesson here is of paramount importance: For accurate cost-performance trade-offs, you must consider all the life-cycle costs associated with design and manufacturing.
Focusing attention on an important design/implementation issue, Swartzlander examines the trade-off between IC size and advanced packaging technologies. He explores the implementation space of a digital signal processor, from VLSI to wafer-scale integration to MCM implementation. The metrics used for comparison include silicon area, substrate area, and power dissipation. An interesting and perhaps counterintuitive result is that (based only on the area metric) the MCM implementation is less expensive but consumes more power.
The so-called known-good-die (KGD) problem is critically important to a system architect considering the trade-offs between bare-die (MCM) technologies and board technologies that use packaged parts. Part of the problem is that testing is usually performed after parts are packaged, and the technology for die testing prior to packaging is neither mature nor pervasive. Consequently, the particular parts required by a system design may or may not be available at any price. More important, determining KGD availability and acquiring specific design information for a part can be a time-consuming process, requiring communication with multiple vendors. Although this information is seemingly essential during the conceptual phase of design, in practice it is often not available until much later. In his article, Truzzi discusses issues of working with bare dies and presents solutions developed by the European Union-funded Good-Die Project. The article makes a case for a central, independent database of die design information that allows the system architect to quickly determine part availability and specifications.
Test is another area affected by the choice of packaging technology. Advanced packaging offers significant challenges to the test engineer. Test strategies that consider the packaging substrates as well as the ICs themselves are necessary to ensure functional systems with acceptable yields. Sasidhar, Alkalai, and Chatterjee describe a design-for-testability approach for a 3D MCM stack that will serve as an experimental flight computer on an upcoming NASA New Millennium technology demonstration flight.
The articles in this issue introduce important questions that developers and designers must address to successfully model systems early in the design process. We believe that system and technological complexity and global competition mandate this style of design process. However, the most important link in the chain is adoption of this methodology by practicing system designers. The success of early modeling and analysis requires participation and buy-in by these engineers. We hope this special issue will generate awareness, consideration, and discussion of these topics in the broader design and test community.
David E. Schimmel is an associate professor in the School of Electrical and Computer Engineering, and a member of the Packaging Research Center, at the Georgia Institute of Technology. His research interests include parallel computer architecture, VLSI design, asynchronous systems, and the impact of packaging technology on systems. He is author or coauthor of more than 30 technical publications. Schimmel received the BSEE and PhD degrees from Cornell University. He is past chair of the Atlanta chapter of the IEEE Computer Society. He is a member of the IEEE, ACM, Tau Beta Pi, and Eta Kappa Nu.
Chryssa Dislis is a senior engineer at Abstract Design Automation, working in the area of formal verification. Previously, she was a lecturer in the Department of Cybernetics, University of Reading, UK. She has worked in design for test and test economics for the past eight years. Her work encompasses ASIC test strategy evaluation and optimization, VLSI boards, and MCMs. She is the author of a book on test economics and more than 30 papers and book chapters, and she copresents the Economics of Test tutorial at the IEEE International Test Conference. Dislis received the BSc in electronic engineering from the University of Sussex, UK, and the PhD in digital systems from Brunel University, UK. She is a member of the Computer Society.