Issue No.02 - April-June (1998 vol.15)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.679209
This paper presents a study on the interaction between HDL synthesis and partitioning for multi-FPGA designs with varying structural characteristics and HDL coding styles. We propose an integrated synthesis and partitioning methodology for multi-FPGA designs and demonstrate that the proper use of integrated HDL synthesis and partitioning methods is crucial to achieving high density multi-FPGA designs.
HDL, FPGA design, synthesis, partitioning
Wen-Jong Fang, Allen C.-H. Wu, "Integrating HDL Synthesis and Partitioning for Multi-FPGA Designs", IEEE Design & Test of Computers, vol.15, no. 2, pp. 65-72, April-June 1998, doi:10.1109/54.679209