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Issue No.02 - April-June (1998 vol.15)
pp: 22-33
<p>As today's market conditions require design organizations to create products in shorter time, there is also a significant change in the product mix due to fast growing markets such as wireless, automotive, multimedia and network applications. The nature of the current market conditions forces design organizations to move into product areas in which they don't have past experience and to design products with higher complexity, lower power, higher performance, better reusability, and lower cost in shorter turn-around time. It is accepted that the traditional RTL design methodologies cannot sustain the needed productivity increase.</p> <p>Behavioral synthesis offers a methodology which promises significant productivity increase by raising the abstraction level of digital design. Behavioral synthesis is a process of mapping an algorithmic description of a computation into a Register-Transfer Level (RTL) implementation. This methodology includes creating an algorithmic behavior, scheduling, allocating resources, sharing resources, creating interconnect, mapping of the algorithmic behavior to structure (binding), and generating finite-state-machine (FSM). During scheduling the cycle-by-cycle execution of each algorithmic statement is decided. The numbers and types of functional units and registers are decided during resource allocation. Multiplexers, tristate drivers, and wires are created to route the values in the data path from their sources to their destinations during the interconnect creation. Finally, an FSM is generated to control data-path elements and the interconnect according to the schedule and bindings.</p>
IC design, digital design, behavorial synthesis, finite-state machines
Kayhan Küçükçakar, Chih-Tung Chen, Jie Gong, Wim Philipsen, Thomas E. Tkacik, "Matisse: An Architectural Design Tool for Commodity ICs", IEEE Design & Test of Computers, vol.15, no. 2, pp. 22-33, April-June 1998, doi:10.1109/54.679205
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