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Interface Design for Core-Based Systems
October-December 1997 (vol. 14 no. 4)
pp. 42-51
Current chips and "systems-on-chips" (SOCs) consist of a number of interacting library components (or cores) expressed in VHDL, Verilog, or other HDLs. Simulation-based HDLs, intended for capturing low-level functionality and timing, may not be ideal for a design methodology that includes inter-component communication protocol design (e.g., deadlock, starvation), architecture selection, integration and test, where timing abstraction and the capability to include real-time dependencies may be the preferred goals. Formal methods may be utilized at the system level to study the abstracted temporal and functional interactions between various RTL (and other) cores (whose actual structure and behavior can be hidden) as part of the design methodology. We describe the role of temporal abstraction in system-on-chip design, and describe its benefits vis-a-vis traditional approaches. Our methodology allows inclusion of of new and legacy components that can be both electronic and mechanical in nature.
Index Terms:
Core interfaces, interface design, legacy cores, timing abstraction, system-level description languages
Citation:
Vijay K. Madisetti, Lan Shen, "Interface Design for Core-Based Systems," IEEE Design & Test of Computers, vol. 14, no. 4, pp. 42-51, Oct.-Dec. 1997, doi:10.1109/54.632880
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