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Shmoo Plotting: The Black Art of IC Testing
July-September 1997 (vol. 14 no. 3)
pp. 90-97

The drive to build better, less expensive products is nearly universal, and it is certainly true in the semiconductor industry. IC vendors fabricated early MOS integrated circuits with PMOS technologies as an alternative to compete with established bipolar circuits. Complex and expensive, bipolar circuits nonetheless exhibited superior performance and were less sensitive to external parameters, such as voltage and temperature. Although inexpensive because it uses relatively inexpensive processes, PMOS suffered unstable MOSFET threshold voltage and poor electron mobility, compared to the later CMOS processes.

Modern test engineers have access to vastly improved ATE and displays, but the principles of Shmoo plotting are the same: to ensure the highest quality product that can be reliably manufactured on the given manufacturing process.

Index Terms:
IC diagnosis, failure analysis, IC testing,
Citation:
Keith Baker, Jos Van Beers, "Shmoo Plotting: The Black Art of IC Testing," IEEE Design & Test of Computers, vol. 14, no. 3, pp. 90-97, July-Sept. 1997, doi:10.1109/54.606005
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