Cores in layout, netlist, and synthesizable register-transfer-level form have become an integral part of chip design methodology. As designers strive to satisfy time-to-market demands for chips with high levels of integration and density, they find that cores and other forms of design reuse are essential. However, designers face many challenges in core testing, in interconnecting cores in a complex chip, and in packaging core-level tests to run on a complete chip. This roundtable brought together representatives from EDA vendors, core suppliers, and design firms to discuss these key issues.

D&T thanks participants R. Chandramouli (LV Software), Sujit Dey (NEC USA), Shankar Hemmady (Guru Technologies), Chit Mallipeddi (Cadence Design Systems), Rochit Rajsuman (Equator Technologies), Ron Walther (IBM), and Yervant Zorian (LogicVision).

D&T gratefully acknowledges the help of Thomas L. Anderson (Phoenix Technologies), our moderator, and Kaushik Roy (Purdue), our Roundtables Editor, who organized the event. Also present were Ken Wagner (S3 Incorporated) and Hyon S. (Ed) Han (Rockwell International), who helped with the roundtable.

D&T thanks the IEEE Computer Society Test Technology Technical Committee (TTTC) for sponsoring this roundtable, which took place during the October 1996 IEEE International Test Conference.