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Issue No.02 - April-June (1997 vol.14)
pp: 40-50
ABSTRACT
<p>Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors.</p>
CITATION
Reinaldo A. Bergamaschi, Salil Raje, "Observable Time Windows: Verifying High-Level Synthesis Results", IEEE Design & Test of Computers, vol.14, no. 2, pp. 40-50, April-June 1997, doi:10.1109/54.587740
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