Issue No.01 - January-March (1997 vol.14)
Published by the IEEE Computer Society
With the 25th anniversary of the microprocessor recently passing, it is fitting for IEEE Design & Test to devote a special issue to these unique devices. Very few inventions in mankind's history have had such a widespread and quick impact on business and society as the microprocessor. Incorporated in products with annual sales of over one trillion dollars, the microprocessor maintains an incredible pace of development, creating industries and companies that would not otherwise exist. Although the business and societal impacts continue to evolve, the microprocessor has already profoundly affected the electrical engineering field itself.
No invention or device has had such a dramatic impact on semiconductors—whether in design, computer-aided design tools, test, verification, or manufacturing methodologies. With performance that doubles every 18 months, microprocessors have been the technology driver behind much of the industry's profits this decade. Once, the DRAM drove the semiconductor business and helped fulfill Moore's law—now, it is the microprocessor.
An oft-used analogy based on an automobile describes the pace of microprocessor development in nontechnical terms. Although told in many forms, the analogy's general point is that if the automobile had progressed as quickly as the microprocessor, the average car would have a top speed of 10,000 miles per hour, get 1,200 miles per gallon, and cost 12 cents!
What these comparisons usually omit, however, is quality. If the auto industry had the same quality levels as those needed to produce today's microprocessors, only 8,000 cars in the United States would need repair each year! Imagine how this would change society—a 12-cent car that the majority of drivers never needed to repair! This auto fantasy translates into reality in the microprocessor world.
Although it is always interesting to see how people live on the leading (or bleeding) edge, can designers of other ICs learn anything useful from microprocessor design techniques? The answer is a resounding yes.
Usually, microprocessor design contends with many challenges a few years earlier than does the general industry. We see this, for example, in the problems confronting deep-submicron design today. The microprocessor teams and their methodologies have confronted the deep-submicron demon the ASIC world talks about and have won the battle.
What does deep-submicron test entail? Open this issue of D&T. How are large, deep-submicron designs verified? How will the manufacturing environment change to ramp production of these designs? What is on the horizon for project management of large designs? Open this issue!
The future holds many challenges in all areas of the design, test, and manufacture of microprocessors. For instance, we must often adapt past methods. Although innovative, microprocessor-based systems have replaced many larger computer systems such as mainframes, the technology producing them seems familiar. Is emulation just a new twist to the breadboarding of years past? Is scan from the mainframe days making a comeback in the tiny devices replacing those "hunks of iron"?
Despite definite changes in 25 years (no one does ruby cutting anymore), the task remains familiar. Just as in the early Intel 4004 development, designers must still deal with first-silicon bugs, find the root cause, spin the mask sets, and get the product shipped. 1
The five articles in this special issue focus on microprocessors and the methodologies used to deliver them to market.
First is a total approach to testability features in the Sun UltraSparc I and II. The article covers the typical design and test issues, but also touches upon the very important issues of debugging and manufacturability. Managing the interplay of these issues is critical to achieving time-to-volume goals for a design.
In a companion article, Youngs and Paramanandam look at one manufacturing issue involved in ramping up production of a typical high-end processor. They describe memory defect mapping and repair—the process, the role of DFT, the information used, and the way they used that information to improve yield and ship the product earlier. This is a great example of the battles that semiconductor companies fight to increase yields and reduce costs.
Bhavsar and Edmondson's article on the DEC Alpha 21164 shows that there is more than one way to solve the high-performance microprocessor test problem. In contrast to the UltraSparc methodology, they advocate a less structured approach and more custom techniques with a dash of BIST. Their efforts demonstrate that DFT doesn't necessarily slow down a design.
Using the Motorola M68060 as an example, Kumar's article presents a common occurrence in the microprocessor business with respect to verification and emulation. Emulation has become a standard tool in many design shops, and the author describes what it takes to perform emulation, how it is typically used, and why. This article sheds light on the effects of emulation in a design process.
Finally, Jacome and Lapinskii address the timely issue of how to plan large projects such as microprocessors. They present an innovative tool that tries to formalize the ad hoc, apprentice nature of project planning. Will tools like this help or replace the project manager? Only time will tell, but it is an interesting step in the right direction. Project planning is a long-neglected area of the design and development process.
These articles, taken together, should give the reader an excellent feel for the various techniques used in designing, verifying, producing, and managing the projects that produce the all-important microprocessor. Often, techniques common in microprocessor design later make their way to the remainder of the design community. Thus, these articles also give a glimpse into the future of IC design.
I trust readers will find this issue valuable in expanding their knowledge not only of microprocessor design and test but also that of any large, deep-submicron devices.
I thank Ken Wagner, Marie English, Janet Wilson, and the reviewers for their hard work and effort in preparing and producing this special issue. It has been a great pleasure to work with you. Finally, I thank the authors for working with me under a tight schedule and taking the time from their many other jobs to write, edit, and rewrite their manuscripts.
Marc E. Levitt is the manager of and senior technical contributor in the Testability Group of Sun Microelectronics, a division of Sun Microsystems Inc. Over the past five years, he has led the testability effort for the UltraSparc I and II series of microprocessors and numerous ASICs. Levitt holds a BS in computer engineering from Lehigh University, Bethlehem, Pennsylvania, and MS and PhD degrees in electrical engineering from the University of Illinois, Urbana. He authored the IEEE Std 1149.1 subset specification for synchronous cache SRAMs that the Joint Electron Device Engineering Council adopted as a standard. The author or coauthor of over 20 refereed publications and three book chapters, he holds five US patents in the areas of DFT, test CAD, and formal verification. He is a member of the IEEE, the Association for Computing Machinery, and the Eta Kappa Nu and Tau Beta Pi honor societies.