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Issue No.04 - Winter (1996 vol.13)
pp: 61-65
ABSTRACT
<p>IDDQ testing has emerged from a company-specific CMOS IC test technology in the 1960's and 1970's to a worldwide-accepted technique that is a requirement for low-defect PPM levels and failure rates. It is the single most sensitive test method to detect CMOS IC defects and an abundance of studies have laid a solid foundation for why this is so.</p> <p>The IDDQ test uses the quiescent power supply current of logic states as an indication of defect presence. Its major requirement for maximum efficiency is that the design implement nanowatt power levels (nanoamp supply current) in the quiescent portion of the power supply current. No direct connections are allowed between VDD and VSS during the quiescent period.</p> <p>IDDQ testing has increased significantly since 1990, highlighting problems and driving solutions not addressed by the high reliability manufacturers of earlier technologies. Faster IDDQ instrumentation and better software tools to generate and grade IDDQ test patterns are a result of this increased interest. Two major issues confronting IDDQ testing are addressed: the yield loss issue and increased background current of deep submicron IC technologies projected by the SIA/Sematech road map. Both issues are points of controversy.</p>
INDEX TERMS
IDDQ testing, IC test technology, CMOS defects, deep-submicron IC test
CITATION
Jerry M. Soden, Charles F. Hawkins, "IDDQ Testing: Issues Present and Future", IEEE Design & Test of Computers, vol.13, no. 4, pp. 61-65, Winter 1996, doi:10.1109/54.544537
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