Issue No.04 - Winter (1996 vol.13)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.544532
This original study concerns one important aspect of FPGA architecture: the design of its interconnect structure. Early SRAM-based FPGAs featured routing channels that consisted mostly of short wire segments. Joining two or more segments via routing switches formed longer segments. Long connections passing through several switches in series, however, produce a large delay. This occurs because pass-transistor switches have significant series resistance and parasitic capacitance. More recent SRAM-based products include wire segments of various lengths, but no previous study has investigated the trade-offs in selecting a particular routing architecture scheme. Since the wire segment lengths available in an FPGA are key to speed performance, this is the central theme of the research reported here.
Architecture, FPGA design, interconnect delays, routing
Stephen Brown, Zvonko Vranesic, "Minimizing FPGA Interconnect Delays", IEEE Design & Test of Computers, vol.13, no. 4, pp. 16-23, Winter 1996, doi:10.1109/54.544532