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Issue No.03 - Fall (1996 vol.13)
pp: 9-11
Published by the IEEE Computer Society
IEEE Design & Test of Computers first published an issue on rapid prototyping in June 1991. That issue focused primarily on design, emulation, and test of chips and ASICs. Many developments since then have revolutionized digital chip synthesis and test; chip level designs often have turnaround times of a few weeks. The current challenge is prototyping and fielding systems of single- and multiboard complexity consisting of common-off-the-shelf (COTS) and ASIC components. Starting from high-level specifications, our goal is to turn such designs around in a few months as opposed to a few years. Concurrent reduction in cost and the capability to include best of practice remain topics of intense industrial interest.
This special issue focuses on rapidly integrating and prototyping COTS and ASIC hardware together with software in cost-effective, board-level platforms, starting from high-level specifications. These electronic systems have a variety of implementation technologies and interfaces and a wide range of real-time data rates. Since this is an extremely broad area, we have chosen an important problem domain—digital signal processing—to provide the necessary focus.
One significant development in this area is the US Department of Defense Rapid Prototyping of Application-Specific Signal Processors (RASSP) program, which began in 1994 under the sponsorship of the Defense Advanced Research Projects Agency's (DARPA's) Electronic Technology Office. RASSP targets the design, prototyping, procurement, and manufacturing of embedded signal-processing subsystems. Systems of interest range from efficiently packaged, single-board, embedded DSP systems to large, multichassis radar signal processors with performance requirements from 20 to 1,000 Gflops at data rates between 50 and 1,000 Mbytes/s.
RASSP is a $150 million research program headed (in separate efforts) by Lockheed-Martin's Advanced Technology Laboratories and Sanders Corporation. Over two dozen other commercial firms, universities, and research organizations also contribute.
Within the past two years, the program has achieved several noteworthy accomplishments, some of which this special issue presents. This issue also includes related developments from elsewhere in the world.
Figure 1 (next page) shows a typical board, consisting of layers of hardware and software interfaces. Board prototyping takes three steps: hardware integration, software integration, and hardware-software integration and system test.


Figure 1. Embedded-system hardware software design, integration, and test.

Hardware integration includes building and configuring the runtime (and real time) deployed platform, designing and installing cabling, configuring each module, and assigning interrupts and memory addresses for each hardware subsystem. The goal of this step is to create a memory map of the entire system and also to deal with packaging issues (such as the use of multichip modules).
Software integration involves developing device drivers and I/O interface libraries to enable communication with the application software. It also includes functional and unit testing of the individual runtime utility and software modules. Finally, designers test the system's various I/O utilities independently of the application software. Successful completion of this task is highly resource (labor and cost) intensive.
During hardware-software integration and system test, designers initially use external test equipment and software to stimulate the prototype in an environment similar to the targeted one. Applying a data pattern will test the appropriate application software action that drives each I/O interface. Designers then completely test the given system's response to both the application and the control software, another extremely labor-intensive task.
Hardware and software prototyping costs are closely related, compounding the difficulties. Analysis of actual designs shows that hardware designs that provide very little margin in CPU cycles or memory greatly increase software prototyping costs, a little-appreciated fact. Tight hardware margins especially make developing control, diagnostic, and test software difficult. Unfortunately, such software typically comprises over 90% of the total. Actual application functionality—often composed in large part of library calls—comprises less than 10% of all software.
Another problem with system synthesis is that the software development cycle depends on the hardware availability (since developing control and diagnostic software requires knowledge of the hardware). This coupling of hardware and software design leads to an expensive and long process. However, a new solution exists: virtual prototyping.
A technology that provides detailed models (and representations) of the system at various levels of design abstraction, virtual prototyping enables designers to rapidly design hardware and software components and interfaces. It also allows testing of the system's compliance to user input requirements and test benches. The focus is thus on building the "right" system, and not the system right. Many of the articles in this issue discuss this new technology, which has been a central focus of the RASSP program.
The first article, by V. Madisetti, presents a detailed model of current industrial practice (circa 1993) in system level design and its associated timelines and costs. This data came from an extensive RASSP Education and Facilitation program survey of leading industrial vendors in 1995. This article also presents several factors that promise technology improvements.
J. Malley describes the RASSP program and the Sanders team's technical approach to further system level design. This article summarizes their methodology and their progress using real examples of large avionics systems developed in the past two years with this methodology.
R. Sedmak and J. Evans describe the results of the Advanced Technology Laboratory's RASSP efforts: a highly automated DFT process that spans the entire product life cycle. Detailed results from case studies demonstrate the effectiveness of their methodology.
L.-R. Dung and V. Madisetti address the efficient performance of front-end design tasks using conceptual prototyping. Such tasks include functional design, partitioning, architecture selection and verification, and communication and interface design. The authors show how to develop complex embedded digital systems in a few weeks using a scalable methodology based on a VHDL model-based simulation environment. This methodology quickly produces initial designs that we may upgrade later as technology improves. Hence, we call this a model year architecture.
System level design using virtual prototyping requires effective use of simulation and models. S. Habinc and P. Sinander describe how to use VHDL effectively in board level simulation of complex systems. They show how to write simulations for high functional and timing accuracy and also for efficient simulation performance. They present several successful industrial activities, clearly demonstrating the importance of their work in electronics systems design.
C. Kuttner describes how to synthesize processors rapidly by using the specific requirements of the application to drive the design process. This effort, also sponsored by DARPA, presents several processor synthesis case studies using a commercial tool that evolved from this research.
Conclusion
These results in design and test of complex digital systems represent a giant step forward in this area of increasing importance. Virtual prototyping is rapidly becoming an accepted technology of importance, yet its success depends on the availability of verified hardware and software models at multiple design abstraction levels. VHDL appears applicable to system level design and test at higher levels of abstraction. Industry can use many of the results presented here immediately and effectively to its advantage. There is much more exciting research than we have room for in this issue. The RASSP server (http://rassp.scra.org) displays links to information on concurrent electronic system design.
It has been our pleasure to work with Ken Wagner, Marie English, Janet Wilson, Margaret Weatherford, and the reviewers of IEEE Design & Test of Computers throughout the preparation and production of this issue, and we thank them for their efforts. We hope readers will find this issue timely and valuable.

Vijay K. Madisetti is an associate professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He is the founder and CEO of VP Technologies Inc., Marietta, Georgia, a subcontractor to avionics organizations in the areas of virtual prototyping and digital system specification, design, simulation, and synthesis. His current interests are in rapid prototyping, VHDL-based simulation and synthesis, and legacy systems upgrade. Madisetti obtained his PhD in electrical engineering and computer science from UC Berkeley. He is a member of the IEEE and the Computer Society. He recently coauthored (with M. Ben Romdhane and J.W. Hines) Quick Turnaround ASIC Design in VHDL: Core-Based Behavioral Synthesis.

Mark A. Richards is currently a principal research engineer in the Sensors and Electromagnetic Applications Laboratory of the Georgia Tech Research Institute. He teaches digital signal processing and radar signal processing, engages in market development, and conducts research in radar imaging and signal processor benchmarking. He was a DARPA program manager for the RASSP project from 1994 to 1995. Richards holds a PhD from the Georgia Tech in electrical engineering. He received a 1993 NASA Group Achievement Award for work on a processor for airborne windshear detection by radar and served as an associate for the IEEE Transactions on Signal Processing. He is a member of the IEEE, and the Eta Kappa Nu and Sigma Xi honor societies.
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