Issue No.02 - Summer (1996 vol.13)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/54.500201
This article provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs), and gives a summary of recent research results in the field. In the survey section, we first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips. The second part of the article gives an overview of the most important research results on FPD architecture over the past six years, and provides suggestions as to features that may be included in future architectures.
Raul San Martin, John P. Knight, "Optimizing Power in ASIC Behavioral Synthesis", IEEE Design & Test of Computers, vol.13, no. 2, pp. 58-70, Summer 1996, doi:10.1109/54.500201