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Issue No.02 - Summer (1996 vol.13)
pp: 18-25
ABSTRACT
Testing Linear Analog Circuits using Time-Domain Response Parameters Diverse design styles and a multitude of response parameters makes analog circuit testing a difficult and expensive process. Currently, these circuits are tested for their functionality, which in the case of linear analog circuits may take the form of verifying among other functions, the frequency response over the specified range of frequencies, and the step response. Fault oriented testing strives to lower this complexity by testing only for the presence of the most probable defects using a small set of highly efficient tests. In this article, we present a simple test generation technique to derive sinusoidal test waveforms which facilitate detection of a large class of faults from the amplitude and phase error (from the good values) of the steady state time response waveform. In addition, we also demonstrate the suitability of saturated ramp waveforms as tests and the use of associated ramp response parameters like delay, rise-time, and overshoot as criteria for detecting faulty behavior. We show that all these parameters can be computed using simple algorithms from closed form expressions of the sinusoidal and ramp response. We demonstrate our strategy using an example and discuss future directions.
INDEX TERMS
analog testing, time-domain, fault simulation, test generation
CITATION
Ashok Balivada, Jin Chen, Jacob A. Abraham, "Analog Testing with Time Response Parameters", IEEE Design & Test of Computers, vol.13, no. 2, pp. 18-25, Summer 1996, doi:10.1109/54.500197
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