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Issue No.02 - Summer (1996 vol.13)
pp: 10-17
ABSTRACT
<p>Switched-current designs are receiving increasing interest within the VLSI community as the technique allowing analogue functions to be implemented on a digital process. In addition, switched-current designs tend to be robust and compatible with the trend for reduced supply voltages. This article describes the design of a novel type of switched-current memory cell with a built-in-self-test option. The cell is digitally controlled and can be used as a building block for a range of analogue functions. A divide-by-two circuit for reference signal generation in algorithmic A-to-D converters is given as an example application.</p> <p>Furthermore, two self-test approaches for these building blocks are described and their effectiveness evaluated. Over 3000 single faults have been simulated in HSPICE to obtain the fault coverage using an open/short fault model. The self-test functions are easy to apply, need only a very small overhead and result in fault coverages up to 95% for shorts and 60% for open-circuits.</p> <p>The analysis of undetected faults revealed that certain circuit structures used in the demonstrators which are common to analogue and mixed-signal designs are practically untestable.</p>
INDEX TERMS
Switched-Current (SI) Design, Built-In Self-Test, BIST, Design-for-Testability, DfT, Fault Simulation, Testability
CITATION
Thomas Olbrich, Andrew Richardson, "Design and Self-Test for Switched-Current Building Blocks", IEEE Design & Test of Computers, vol.13, no. 2, pp. 10-17, Summer 1996, doi:10.1109/54.500196
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