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Fast Power Estimation of Large Circuits
Spring 1996 (vol. 13 no. 1)
pp. 70-78

Logic-level circuit optimization for low power requires efficient estimation of the power consumed by the resulting circuit. In CMOS, the power consumption depends on the number of transitions occurring on the signals internal to a circuit. We introduce a new technique to estimate the transition probabilities for internal signals of combinational circuits. This technique uses Markov chains and the concept of reconvergence regions, and is efficiently implemented based on ROBDDs.

The temporal dependence of each signal, multiple concurrent transitions and mutual dependence of internal signals are taken into account. Our technique provides an exact computation for small circuits and an approximate estimation for large circuits. Experimental results show the approximate estimation to be fast even for large circuits while only small inaccuracies appear.

Index Terms:
Low-power design, Markov chains, circuit design, logic level circuit design, CMOS technology
Citation:
Peter H. Schneider, Ulf Schlichtmann, Bernd Wurth, "Fast Power Estimation of Large Circuits," IEEE Design & Test of Computers, vol. 13, no. 1, pp. 70-78, Spring 1996, doi:10.1109/54.485785
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