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Issue No.01 - Spring (1996 vol.13)
pp: 16-25
ABSTRACT
This article surveys research activities in on-line hardware-checking techniques developed in Eastern Europe including the former Soviet Union. It presents some interesting results on self-checking circuit design, many of which are unknown to Western researchers as they appeared in not-so-widely known journals and conference proceedings. Much of the work is new and is judged to be a significant contribution to the field. Among the traditional designs intended for synchronous circuits are some state-of-the-art self-testing checkers, new error detecting unordered codes that are an extension of Berger codes, self-checking combinational circuits using parity, and several designs of totally self-checking synchronous sequential circuits. Included also are the first-ever design concepts of totally self-checking asynchronous circuits.
INDEX TERMS
Concurrent error detection, easily testable circuit, error detecting codes, self-checking circuits, self-testing
CITATION
Stanislaw J. Piestrak, "Self-Checking Design in Eastern Europe", IEEE Design & Test of Computers, vol.13, no. 1, pp. 16-25, Spring 1996, doi:10.1109/54.485779
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