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Issue No.04 - Winter (1995 vol.12)
pp: 52-59
ABSTRACT
<p>We present a partial scan approach, which aims at reducing both area overhead and performance degradation caused by test logic. Given a target speed and an initial design that meets the target, the algorithm selects a minimum set of scan flip-flops, if they exist, that (1) will break all sequential cycles and (2) will not violate the performance requirement after the scan logic is added. If such a set does not exist, the algorithm will find a set of scan flip-flops in which (1) all sequential cycles are broken and (2) the total area increase caused by the scan logic and the subsequent performance optimization to meet the target speed is minimized.</p> <p>Experimental results on some of the ISCAS'89 sequential circuits are presented as well as comparisons between the new method and the existing methods. For circuits synthesized by automatic synthesis tools, we suggest a new design flow, which selects/inserts the partial scan logic after area optimization, but before performance optimization. For meeting both performance and testability requirements, the new design flow tends to produce designs with less area increase than the traditional design flow, which considers testability and adds test logic after performance optimization.</p> <p>This work represents an important concept for considering the three major design parameters, namely, performance, area, and testability, together during the synthesis phase for obtaining the right partial scan solution.</p>
INDEX TERMS
Test algorithms, partial scan, test synthesis, design for test
CITATION
Jing-yang Jou, Kwang-ting (tim) Cheng, "Timing-Driven Partial Scan", IEEE Design & Test of Computers, vol.12, no. 4, pp. 52-59, Winter 1995, doi:10.1109/MDT.1995.473313
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