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Testing Defects in Scan Chains
Winter 1995 (vol. 12 no. 4)
pp. 45-51
ASCII Text
x 
 
Manoj Sachdev, "Testing Defects in Scan Chains," IEEE Design & Test of Computers, vol. 12, no. 4, pp. 45-51, Winter, 1995.
 
 
BibTex
x
 
@article{ 10.1109/MDT.1995.473312,
author = {Manoj Sachdev},
title = {Testing Defects in Scan Chains},
journal ={IEEE Design & Test of Computers},
volume = {12},
number = {4},
issn = {0740-7475},
year = {1995},
pages = {45-51},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.1995.473312},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design & Test of Computers
TI - Testing Defects in Scan Chains
IS - 4
SN - 0740-7475
SP45
EP51
EPD - 45-51
A1 - Manoj Sachdev,
PY - 1995
VL - 12
JA - IEEE Design & Test of Computers
ER -
 

Applying scan-based DFT, IDDQ testing, or both to sequential circuits does not ensure bridging-fault detection, which depends on the resistance of the fault and circuit level parameters. With a “transparent” scan chain, however, the tester can use both methods to detect manufacturing process defects effectively—including difficult-to-detect shorts in the scan chain. The author presents a strategy for making the scan chain transparent. The test complexity of such a chain is very small, regardless of the number of flip-flops it contains.

Citation:
Manoj Sachdev, "Testing Defects in Scan Chains," IEEE Design & Test of Computers, vol. 12, no. 4, pp. 45-51, Winter 1995, doi:10.1109/MDT.1995.473312
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