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Issue No.04 - Winter (1995 vol.12)
pp: 45-51
ABSTRACT
<p>Applying scan-based DFT, I<sub>DDQ</sub> testing, or both to sequential circuits does not ensure bridging-fault detection, which depends on the resistance of the fault and circuit level parameters. With a “transparent” scan chain, however, the tester can use both methods to detect manufacturing process defects effectively—including difficult-to-detect shorts in the scan chain. The author presents a strategy for making the scan chain transparent. The test complexity of such a chain is very small, regardless of the number of flip-flops it contains.</p>
CITATION
Manoj Sachdev, "Testing Defects in Scan Chains", IEEE Design & Test of Computers, vol.12, no. 4, pp. 45-51, Winter 1995, doi:10.1109/MDT.1995.473312
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